From 367ad5aee76228916677acf2937f6f1c346686ea Mon Sep 17 00:00:00 2001 From: whitequark Date: Tue, 9 Jul 2019 02:44:03 +0000 Subject: [PATCH] build.dsl: add Resource.family abstraction. --- nmigen/build/dsl.py | 14 ++++++++++++++ nmigen/test/test_build_dsl.py | 9 +++++++++ 2 files changed, 23 insertions(+) diff --git a/nmigen/build/dsl.py b/nmigen/build/dsl.py index a3e4a58..d5d181e 100644 --- a/nmigen/build/dsl.py +++ b/nmigen/build/dsl.py @@ -181,6 +181,20 @@ class Subsignal: class Resource(Subsignal): + @classmethod + def family(cls, name_or_number, number=None, *, ios, default_name): + # This constructor accepts two different forms: + # 1. Number-only form: + # Resource.family(0, default_name="name", ios=[Pins("A0 A1")]) + # 2. Name-and-number (name override) form: + # Resource.family("override", 0, default_name="name", ios=...) + # This makes it easier to build abstractions for resources, e.g. an SPIResource abstraction + # could simply delegate to `Resource.family(*args, default_name="spi", ios=ios)`. + if number is None: # name_or_number is number + return cls(default_name, name_or_number, *ios) + else: # name_or_number is name + return cls(name_or_number, number, *ios) + def __init__(self, name, number, *args): super().__init__(name, *args) diff --git a/nmigen/test/test_build_dsl.py b/nmigen/test/test_build_dsl.py index c8f95ab..d7c73b9 100644 --- a/nmigen/test/test_build_dsl.py +++ b/nmigen/test/test_build_dsl.py @@ -225,6 +225,15 @@ class ResourceTestCase(FHDLTestCase): " (subsignal rx (pins i A1))" " (attrs IOSTANDARD=LVCMOS33))") + def test_family(self): + ios = [Subsignal("clk", Pins("A0", dir="o"))] + r1 = Resource.family(0, default_name="spi", ios=ios) + r2 = Resource.family("spi_flash", 0, default_name="spi", ios=ios) + self.assertEqual(r1.name, "spi") + self.assertEqual(r1.ios, ios) + self.assertEqual(r2.name, "spi_flash") + self.assertEqual(r2.ios, ios) + class ConnectorTestCase(FHDLTestCase): def test_string(self): -- 2.30.2