From 368583227251abba9ec40a1050557d1944d9feda Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Tue, 9 Jan 2024 12:54:03 +0000 Subject: [PATCH] ls011: Remove duplicate Fixed-point Load with Post-Update entries --- openpower/sv/rfc/ls011.mdwn | 296 +----------------------------------- 1 file changed, 1 insertion(+), 295 deletions(-) diff --git a/openpower/sv/rfc/ls011.mdwn b/openpower/sv/rfc/ls011.mdwn index 9137b5d27..5742d7957 100644 --- a/openpower/sv/rfc/ls011.mdwn +++ b/openpower/sv/rfc/ls011.mdwn @@ -195,301 +195,7 @@ where the same pseudocode for `lbzu` is: Add the following additional Section to Fixed-Point Load: Book I 3.3.2.1 -## Load Byte and Zero with Post-Update - -D-Form - -``` - |0 |6 |9 |10 |11 |16 |31 | - | PO | RT | RA| D | -``` - -* lbzup RT,D(RA) - -Pseudo-code: - -``` - EA <- (RA) - RT <- ([0] * (XLEN-8)) || MEM(EA, 1) - RA <- (RA) + EXTS(D) -``` - -Let the effective address (EA) be (RA|0). -The byte in storage addressed by EA is loaded into -RT[56:63]. RT[0:55] are set to 0. - -The sum (RA|0)+D is placed into register RA. - -If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -## Load Byte and Zero with Post-Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RT | RA | RB | XO | / | -``` - -* lbzupx RT,RA,RB - -Pseudo-code: - -``` - EA <- (RA) - RT <- ([0] * (XLEN-8)) || MEM(EA, 1) - RA <- (RA) + (RB) -``` - -Let the effective address (EA) be (RA). -The byte in storage addressed by EA is loaded into -RT[56:63]. RT[0:55] are set to 0. - -The sum (RA)+(RB) is placed into register RA. - -If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -## Load Halfword and Zero with Post-Update - -D-Form - -``` - |0 |6 |9 |10 |11 |16 |31 | - | PO | RT | RA| D | -``` - -* lhzup RT,D(RA) - -Pseudo-code: - -``` - EA <- (RA) - RT <- ([0] * (XLEN-16)) || MEM(EA, 2) - RA <- (RA) + EXTS(D) -``` - -Let the effective address (EA) be (RA|0). -The halfword in storage addressed by EA is loaded into -RT[48:63]. RT[0:47] are set to 0. - -The sum (RA|0)+D is placed into register RA. - -If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -## Load Halfword and Zero with Post-Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RT | RA | RB | XO | / | -``` - -* lhzupx RT,RA,RB - -Pseudo-code: - -``` - EA <- (RA) - RT <- ([0] * (XLEN-16)) || MEM(EA, 2) - RA <- (RA) + (RB) -``` - -Let the effective address (EA) be (RA). -The halfword in storage addressed by EA is loaded into -RT[48:63]. RT[0:47] are set to 0. - -The sum (RA)+(RB) is placed into register RA. - -If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -## Load Halfword Algebraic with Post-Update - -D-Form - -``` - |0 |6 |9 |10 |11 |16 |31 | - | PO | RT | RA| D | -``` - -* lhaup RT,D(RA) - -Pseudo-code: - -``` - EA <- (RA) - RT <- EXTS(MEM(EA, 2)) - RA <- (RA) + EXTS(D) -``` - -Special Registers Altered: - - None - -## Load Halfword Algebraic with Post-Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RT | RA | RB | XO | / | -``` - -* lhaupx RT,RA,RB - -Pseudo-code: - -``` - EA <- (RA) - RT <- EXTS(MEM(EA, 2)) - RA <- (RA) + (RB) -``` - -Special Registers Altered: - - None - -## Load Word and Zero with Post-Update - -D-Form - -``` - |0 |6 |9 |10 |11 |16 |31 | - | PO | RT | RA| D | -``` - -* lwzup RT,D(RA) - -Pseudo-code: - -``` - EA <- (RA) - RT <- [0]*32 || MEM(EA, 4) - RA <- (RA) + EXTS(D) -``` - -Let the effective address (EA) be (RA|0). -The word in storage addressed by EA is loaded into -RT[32:63]. RT[0:31] are set to 0. - -The sum (RA|0)+D is placed into register RA. - -If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -## Load Word and Zero with Post-Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RT | RA | RB | XO | / | -``` - -* lwzupx RT,RA,RB - -Pseudo-code: - -``` - EA <- (RA) - RT <- [0] * 32 || MEM(EA, 4) - RA <- (RA) + (RB) -``` - -Let the effective address (EA) be (RA). -The word in storage addressed by EA is loaded into -RT[32:63]. RT[0:31] are set to 0. - -The sum (RA)+(RB) is placed into register RA. - -If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -## Load Word Algebraic with Post-Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RT | RA | RB | XO | / | -``` - -* lwaupx RT,RA,RB - -Pseudo-code: - -``` - EA <- (RA) - RT <- EXTS(MEM(EA, 4)) - RA <- (RA) + (RB) -``` - -Special Registers Altered: - - None - -## Load Doubleword with Post-Update Indexed - -DS-Form - -* ldup RT,DS(RA) - -Pseudo-code: - -``` - EA <- (RA) - RT <- MEM(EA, 8) - RA <- (RA) + EXTS(DS || 0b00) -``` - -Special Registers Altered: - - None - -## Load Doubleword with Post-Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RT | RA | RB | XO | / | -``` - -* ldupx RT,RA,RB - -Pseudo-code: - -``` - EA <- (RA) - RT <- MEM(EA, 8) - RA <- (RA) + (RB) -``` - -Special Registers Altered: - - None +TODO: move the inline import to pifixedload here... (separate commit). ----- -- 2.30.2