From 368b25021e586ab542ccec13ad5659ea34342919 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 5 Jun 2022 05:30:33 +0100 Subject: [PATCH] --- openpower/sv/fclass.mdwn | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openpower/sv/fclass.mdwn b/openpower/sv/fclass.mdwn index 64c432e9f..6bc8f6263 100644 --- a/openpower/sv/fclass.mdwn +++ b/openpower/sv/fclass.mdwn @@ -1,8 +1,6 @@ # fclass -In SV just as with [[sv/fcvt]] single precision is to be considered half-of-elwidth precision. Thus when elwidth=FP32 fptstsp will test half that precision, at FP16. - -based on xvtstdcsp v3.0B p768 the instruction performs analysis of the FP number to determine if it is Infinity, NaN, Denormalised or Zero and if so which sign. +based on xvtstdcsp v3.0B p768 the instruction performs analysis of the FP number to determine if it is Infinity, NaN, Denormalised or Zero and if so which sign. When VSX is not implemented these instructions become necessary. unlike xvtstdcsp the result is stored in a Condition Register Field specified by BF. @@ -48,3 +46,6 @@ exponent <- src[1:11] fraction <- src[12:63] exponent & 7FF ``` + +In SV just as with [[sv/fcvt]] single precision is to be considered half-of-elwidth precision. Thus when elwidth=FP32 fptstsp will test half that precision, at FP16. + -- 2.30.2