From 3698f3d3dfd24e10f6abaff08a28af5f88d94dd1 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Sun, 19 Jul 2020 20:15:25 -0700 Subject: [PATCH] fix mismatched comb process delays --- src/ieee754/div_rem_sqrt_rsqrt/test_core.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py index 073396cd..d7aeded6 100755 --- a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py @@ -275,6 +275,8 @@ class TestDivPipeCore(unittest.TestCase): gtkw_file=open(f"{base_name}.gtkw", "w"), traces=[*dut.traces()]): def generate_process(): + if not sync: + yield Delay(1e-6) for test_case in test_cases: if sync: yield Tick() @@ -313,7 +315,7 @@ class TestDivPipeCore(unittest.TestCase): str(test_case)) if sync: sim.add_clock(2e-6) - silent = False + silent = True sim.add_process(trace_process(generate_process, "generate:", silent=silent)) sim.add_process(trace_process(check_process, "check:", silent=silent)) sim.run() -- 2.30.2