From 36ab8ef4e7b69f9db0fd3299d976a9195a063512 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Thu, 21 Jan 2021 12:45:24 +0000 Subject: [PATCH] dev: Consistently use ISO prefixes We currently use the traditional SI-like prefixes for to represent binary multipliers in some contexts. This is ambiguous in many cases since they overload the meaning of the SI prefix. Here are some examples of commonly used in the industry: * Storage vendors define 1 MB as 10**6 bytes * Memory vendors define 1 MB as 2**20 bytes * Network equipment treats 1Mbit/s as 10**6 bits/s * Memory vendors define 1Mbit as 2**20 bits In practice, this means that a FLASH chip on a storage bus uses decimal prefixes, but that same flash chip on a memory bus uses binary prefixes. It would also be reasonable to assume that the contents of a 1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet link. That's however not the case due to different meanings of the prefix. The quantity 2MX is treated differently by gem5 depending on the unit X: * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes. * Interconnect and NoC bandwidths (B/s) use binary prefixes. * Network bandwidths (bps) use decimal prefixes. * Memory sizes and storage sizes (B) use binary prefixes. Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes for binary multipliers for parameters and comments where appropriate. Change-Id: I6ab03934af850494d95a37dcda5c2000794b4d3a Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39578 Reviewed-by: Richard Cooper Reviewed-by: Daniel Carvalho Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/dev/net/Ethernet.py | 31 ++++++++++++++++--------------- src/dev/pci/CopyEngine.py | 4 ++-- src/dev/x86/Pc.py | 4 ++-- 3 files changed, 20 insertions(+), 19 deletions(-) diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py index dd878e295..e5c5562f0 100644 --- a/src/dev/net/Ethernet.py +++ b/src/dev/net/Ethernet.py @@ -92,10 +92,11 @@ class EtherSwitch(SimObject): type = 'EtherSwitch' cxx_header = "dev/net/etherswitch.hh" dump = Param.EtherDump(NULL, "dump object") - fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed in bits " - "per second") + fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed in " + "bits per second") interface = VectorEtherInt("Ethernet Interface") - output_buffer_size = Param.MemorySize('1MB', "size of output port buffers") + output_buffer_size = Param.MemorySize('1MiB', + "size of output port buffers") delay = Param.Latency('0us', "packet transmit delay") delay_var = Param.Latency('0ns', "packet transmit delay variability") time_to_live = Param.Latency('10ms', "time to live of MAC address maping") @@ -139,8 +140,8 @@ class IGbE(EtherDevice): cxx_header = "dev/net/i8254xGBe.hh" hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") - rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO") - tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO") + rx_fifo_size = Param.MemorySize('384KiB', "Size of the rx FIFO") + tx_fifo_size = Param.MemorySize('384KiB', "Size of the tx FIFO") rx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache") tx_desc_cache_size = Param.Int(64, @@ -152,7 +153,7 @@ class IGbE(EtherDevice): SubClassCode = 0x00 ClassCode = 0x02 ProgIF = 0x00 - BAR0 = PciMemBar(size='128kB') + BAR0 = PciMemBar(size='128KiB') MaximumLatency = 0x00 MinimumGrant = 0xff InterruptLine = 0x1e @@ -195,8 +196,8 @@ class EtherDevBase(EtherDevice): rx_delay = Param.Latency('1us', "Receive Delay") tx_delay = Param.Latency('1us', "Transmit Delay") - rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo") - tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo") + rx_fifo_size = Param.MemorySize('512KiB', "max size of rx fifo") + tx_fifo_size = Param.MemorySize('512KiB', "max size of tx fifo") rx_filter = Param.Bool(True, "Enable Receive Filter") intr_delay = Param.Latency('10us', "Interrupt propagation delay") @@ -218,7 +219,7 @@ class NSGigE(EtherDevBase): SubClassCode = 0x00 ClassCode = 0x02 ProgIF = 0x00 - BARs = (PciIoBar(size='256B'), PciMemBar(size='4kB')) + BARs = (PciIoBar(size='256B'), PciMemBar(size='4KiB')) MaximumLatency = 0x34 MinimumGrant = 0xb0 InterruptLine = 0x1e @@ -232,12 +233,12 @@ class Sinic(EtherDevBase): cxx_header = "dev/net/sinic.hh" rx_max_copy = Param.MemorySize('1514B', "rx max copy") - tx_max_copy = Param.MemorySize('16kB', "tx max copy") + tx_max_copy = Param.MemorySize('16KiB', "tx max copy") rx_max_intr = Param.UInt32(10, "max rx packets per interrupt") - rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold") - rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold") - tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold") - tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold") + rx_fifo_threshold = Param.MemorySize('384KiB', "rx fifo high threshold") + rx_fifo_low_mark = Param.MemorySize('128KiB', "rx fifo low threshold") + tx_fifo_high_mark = Param.MemorySize('384KiB', "tx fifo high threshold") + tx_fifo_threshold = Param.MemorySize('128KiB', "tx fifo low threshold") virtual_count = Param.UInt32(1, "Virtualized SINIC") zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold") zero_copy_threshold = Param.UInt32(256, @@ -252,7 +253,7 @@ class Sinic(EtherDevBase): SubClassCode = 0x00 ClassCode = 0x02 ProgIF = 0x00 - BARs = PciMemBar(size='64kB') + BARs = PciMemBar(size='64KiB') MaximumLatency = 0x34 MinimumGrant = 0xb0 InterruptLine = 0x1e diff --git a/src/dev/pci/CopyEngine.py b/src/dev/pci/CopyEngine.py index f5a0f9ee7..62d9bd71f 100644 --- a/src/dev/pci/CopyEngine.py +++ b/src/dev/pci/CopyEngine.py @@ -48,10 +48,10 @@ class CopyEngine(PciDevice): InterruptLine = 0x20 InterruptPin = 0x01 - BAR0 = PciMemBar(size='1kB') + BAR0 = PciMemBar(size='1KiB') ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device") - XferCap = Param.MemorySize('4kB', + XferCap = Param.MemorySize('4KiB', "Number of bits of transfer size that are supported") latBeforeBegin = Param.Latency('20ns', diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py index 0ed264854..736f068fd 100644 --- a/src/dev/x86/Pc.py +++ b/src/dev/x86/Pc.py @@ -41,7 +41,7 @@ def x86IOAddress(port): class PcPciHost(GenericPciHost): conf_base = 0xC000000000000000 - conf_size = "16MB" + conf_size = "16MiB" pci_pio_base = 0x8000000000000000 @@ -70,7 +70,7 @@ class Pc(Platform): default_bus = IOXBar() # A device to handle accesses to unclaimed IO ports. - empty_isa = IsaFake(pio_addr=x86IOAddress(0), pio_size='64kB', + empty_isa = IsaFake(pio_addr=x86IOAddress(0), pio_size='64KiB', ret_data8=0, ret_data16=0, ret_data32=0, ret_data64=0, pio=default_bus.mem_side_ports) -- 2.30.2