From 36af6a79c0e9c43440d034b299de2e9cbe3b5deb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 11 Apr 2020 10:26:13 +0100 Subject: [PATCH] pass and lock immediate in --- libreriscv | 2 +- src/soc/experiment/compalu.py | 12 +++++------- src/soc/experiment/sim.py | 1 + 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/libreriscv b/libreriscv index 999e7155..29219bd5 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit 999e7155eb5811b4fae733aa63328ca07a4da3d3 +Subproject commit 29219bd53d45768c6f57a876a78c5758b29bd7d1 diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py index d0fe6aa3..0937b016 100644 --- a/src/soc/experiment/compalu.py +++ b/src/soc/experiment/compalu.py @@ -57,7 +57,6 @@ class ComputationUnitNoDelay(Elaboratable): # operation / data input self.oper_i = CompALUOpSubset() # operand - self.imm_i = self.oper_i.imm_data # immediate in self.src1_i = Signal(rwid, reset_less=True) # oper1 in self.src2_i = Signal(rwid, reset_less=True) # oper2 in @@ -109,11 +108,12 @@ class ComputationUnitNoDelay(Elaboratable): # select immediate if opcode says so. however also change the latch # to trigger *from* the opcode latch instead. - op_is_imm = self.imm_i.imm_ok + op_is_imm = oper_r.imm_data.imm_ok src2_or_imm = Signal(self.rwid, reset_less=True) src_sel = Signal(reset_less=True) m.d.comb += src_sel.eq(Mux(op_is_imm, opc_l.q, src_l.q)) - m.d.comb += src2_or_imm.eq(Mux(op_is_imm, self.imm_i.imm, self.src2_i)) + m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, + self.src2_i)) # create a latch/register for src1/src2 latchregister(m, self.src1_i, self.alu.a, src_l.q) @@ -168,16 +168,14 @@ class ComputationUnitNoDelay(Elaboratable): def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0): - yield dut.issue_i.eq(1) - yield yield dut.issue_i.eq(0) yield yield dut.src1_i.eq(a) yield dut.src2_i.eq(b) yield dut.oper_i.insn_type.eq(op) yield dut.oper_i.invert_a.eq(inv_a) - yield dut.imm_i.imm.eq(imm) - yield dut.imm_i.imm_ok.eq(imm_ok) + yield dut.oper_i.imm_data.imm.eq(imm) + yield dut.oper_i.imm_data.imm_ok.eq(imm_ok) yield dut.issue_i.eq(1) yield yield dut.issue_i.eq(0) diff --git a/src/soc/experiment/sim.py b/src/soc/experiment/sim.py index a96f90a8..1c725b25 100644 --- a/src/soc/experiment/sim.py +++ b/src/soc/experiment/sim.py @@ -36,6 +36,7 @@ class RegSim: self.regs = [0] * nregs def op(self, op, op_imm, imm, src1, src2, dest): + print ("regsim op src1, src2", op, op_imm, imm, src1, src2, dest) maxbits = (1 << self.rwidth) - 1 src1 = self.regs[src1] & maxbits if op_imm: -- 2.30.2