From 36b34aa4a9f09d0d9bb66fba00ac58cc7e4fe11b Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Thu, 10 Oct 1996 16:28:14 +0000 Subject: [PATCH] * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM into [AD][MN][01] for encoding the position of the register in the opcode. Matsushita. --- opcodes/ChangeLog | 6 + opcodes/mn10300-opc.c | 412 ++++++++++++++++++++++-------------------- 2 files changed, 218 insertions(+), 200 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a3293ddbb49..5dc325bfa19 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM + into [AD][MN][01] for encoding the position of the register + in the opcode. + Wed Oct 9 11:19:26 1996 Jeffrey A Law (law@cygnus.com) * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions, diff --git a/opcodes/mn10300-opc.c b/opcodes/mn10300-opc.c index 7d5d833fdd3..f83edb2f2a9 100644 --- a/opcodes/mn10300-opc.c +++ b/opcodes/mn10300-opc.c @@ -38,19 +38,31 @@ const struct mn10300_operand mn10300_operands[] = { #define UNUSED 0 {0, 0, 0}, -#define DN (UNUSED+1) +#define DN0 (UNUSED+1) {2, 0, MN10300_OPERAND_DREG}, -#define DM (DN+1) +#define DN1 (DN0+1) + {2, 2, MN10300_OPERAND_DREG}, + +#define DM0 (DN1+1) {2, 0, MN10300_OPERAND_DREG}, -#define AN (DM+1) +#define DM1 (DM0+1) + {2, 2, MN10300_OPERAND_DREG}, + +#define AN0 (DM1+1) {2, 0, MN10300_OPERAND_AREG}, -#define AM (AN+1) +#define AN1 (AN0+1) + {2, 2, MN10300_OPERAND_AREG}, + +#define AM0 (AN1+1) {2, 0, MN10300_OPERAND_AREG}, -#define IMM8 (AM+1) +#define AM1 (AM0+1) + {2, 2, MN10300_OPERAND_AREG}, + +#define IMM8 (AM1+1) {8, 0, MN10300_OPERAND_PROMOTE}, #define IMM16 (IMM8+1) @@ -126,198 +138,198 @@ const struct mn10300_operand mn10300_operands[] = { sorted by major opcode. */ const struct mn10300_opcode mn10300_opcodes[] = { -{ "mov", 0x8000, 0xf000, FMT_S1, {SIMM8, DN}}, -{ "mov", 0x80, 0xf0, FMT_S0, {DM, DN}}, -{ "mov", 0xf1e0, 0xfff0, FMT_D0, {DM, AN}}, -{ "mov", 0xf1d0, 0xfff0, FMT_D0, {AM, DN}}, -{ "mov", 0x9000, 0xf000, FMT_S1, {IMM8, AN}}, -{ "mov", 0x90, 0xf0, FMT_S0, {AM, AN}}, -{ "mov", 0x3c, 0xfc, FMT_S0, {SP, AN}}, -{ "mov", 0xf2f0, 0xfff3, FMT_D0, {AM, SP}}, -{ "mov", 0xf2e4, 0xfffc, FMT_D0, {PSW, DN}}, -{ "mov", 0xf2f3, 0xfff3, FMT_D0, {DM, PSW}}, -{ "mov", 0xf2e0, 0xfffc, FMT_D0, {MDR, DN}}, -{ "mov", 0xf2f2, 0xfff3, FMT_D0, {DM, MDR}}, -{ "mov", 0x70, 0xf0, FMT_S0, {MEM(AM), DN}}, -{ "mov", 0xf80000, 0xfff000, FMT_D1, {MEM2(SD8, AM), DN}}, -{ "mov", 0xfa000000, 0xfff00000, FMT_D2, {MEM2(SD16, AM), DN}}, -{ "mov", 0xfc000000, 0xfff00000, FMT_D4, {MEM2(D32, AM), DN}}, -{ "mov", 0x5800, 0xfc00, FMT_S1, {MEM2(D8, SP), DN}}, -{ "mov", 0xfab40000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN}}, -{ "mov", 0xfcb40000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN}}, -{ "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM), DN}}, -{ "mov", 0x300000, 0xfc0000, FMT_S2, {MEM(ABS16), DN}}, -{ "mov", 0xfca40000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN}}, -{ "mov", 0xf000, 0xfff0, FMT_D0, {MEM(AM), AN}}, -{ "mov", 0xf82000, 0xfff000, FMT_D1, {MEM2(D8, AM), AN}}, -{ "mov", 0xfa200000, 0xfff00000, FMT_D2, {MEM2(D16, AM), AN}}, -{ "mov", 0xfc200000, 0xfff00000, FMT_D4, {MEM2(D32, AM), AN}}, -{ "mov", 0x5c00, 0xfc00, FMT_S1, {MEM2(D8, SP), AN}}, -{ "mov", 0xfab00000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), AN}}, -{ "mov", 0xfcb00000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), AN}}, -{ "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM), AN}}, -{ "mov", 0xfaa00000, 0xfffc0000, FMT_D2, {MEM(ABS16), AN}}, -{ "mov", 0xfca00000, 0xfffc0000, FMT_D4, {MEM(ABS32), AN}}, -{ "mov", 0xf8f000, 0xfffc00, FMT_D1, {MEM2(SD8N, AM), SP}}, -{ "mov", 0x60, 0xf0, FMT_S0, {DM, MEM(AN)}}, -{ "mov", 0xf81000, 0xfff000, FMT_D1, {DM, MEM2(SD8, AN)}}, -{ "mov", 0xfa100000, 0xfff00000, FMT_D2, {DM, MEM2(SD16, AN)}}, -{ "mov", 0xfc100000, 0xfff00000, FMT_D4, {DM, MEM2(D32, AN)}}, -{ "mov", 0x4200, 0xf300, FMT_S1, {DM, MEM2(D8, SP)}}, -{ "mov", 0xfa910000, 0xfff30000, FMT_D2, {DM, MEM2(D16, SP)}}, -{ "mov", 0xfc910000, 0xfff30000, FMT_D4, {DM, MEM2(D32, SP)}}, -{ "mov", 0xf340, 0xffc0, FMT_D0, {DM, MEM2(DI, AN)}}, -{ "mov", 0x010000, 0xf30000, FMT_S2, {DM, MEM(ABS16)}}, -{ "mov", 0xfc810000, 0xfff30000, FMT_D4, {DM, MEM(ABS32)}}, -{ "mov", 0xf010, 0xfff0, FMT_D0, {AM, MEM(AN)}}, -{ "mov", 0xf83000, 0xfff000, FMT_D1, {AM, MEM2(SD8, AN)}}, -{ "mov", 0xfa300000, 0xfff00000, FMT_D2, {AM, MEM2(SD16, AN)}}, -{ "mov", 0xfc300000, 0xfff00000, FMT_D4, {AM, MEM2(D32, AN)}}, -{ "mov", 0x4300, 0xf300, FMT_S1, {AM, MEM2(D8, SP)}}, -{ "mov", 0xfa900000, 0xfff30000, FMT_D2, {AM, MEM2(D16, SP)}}, -{ "mov", 0xfc900000, 0xfc930000, FMT_D4, {AM, MEM2(D32, SP)}}, -{ "mov", 0xf3c0, 0xffc0, FMT_D0, {AM, MEM2(DI, AN)}}, -{ "mov", 0xfa800000, 0xfff30000, FMT_D2, {AM, MEM(ABS16)}}, -{ "mov", 0xfc800000, 0xfff30000, FMT_D4, {AM, MEM(ABS32)}}, -{ "mov", 0xf8f400, 0xfffc00, FMT_D1, {SP, MEM2(SD8N, AN)}}, -{ "mov", 0x2c0000, 0xfc0000, FMT_S2, {SIMM16, DN}}, -{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, DN}}, -{ "mov", 0x240000, 0xfc0000, FMT_S2, {IMM16, AN}}, -{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, AN}}, - -{ "movbu", 0xf040, 0xfff0, FMT_D0, {MEM(AM), DN}}, -{ "movbu", 0xf84000, 0xfff000, FMT_D1, {MEM2(SD8, AM), DN}}, -{ "movbu", 0xfa400000, 0xfff00000, FMT_D2, {MEM2(SD16, AM), DN}}, -{ "movbu", 0xfc400000, 0xfff00000, FMT_D4, {MEM2(D32, AM), DN}}, -{ "movbu", 0xf8b800, 0xfffc00, FMT_D1, {MEM2(D8, SP), DN}}, -{ "movbu", 0xfab80000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN}}, -{ "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN}}, -{ "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM), DN}}, -{ "movbu", 0x340000, 0xfc0000, FMT_S2, {MEM(ABS16), DN}}, -{ "movbu", 0xfca80000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN}}, -{ "movbu", 0xf050, 0xfff0, FMT_D0, {DM, MEM(AN)}}, -{ "movbu", 0xf85000, 0xfff000, FMT_D1, {DM, MEM2(SD8, AN)}}, -{ "movbu", 0xfa500000, 0xfff00000, FMT_D2, {DM, MEM2(SD16, AN)}}, -{ "movbu", 0xfc500000, 0xfff00000, FMT_D4, {DM, MEM2(D32, AN)}}, -{ "movbu", 0xf89200, 0xfff300, FMT_D1, {DM, MEM2(D8, SP)}}, -{ "movbu", 0xfa920000, 0xfff30000, FMT_D2, {DM, MEM2(D16, SP)}}, -{ "movbu", 0xfc920000, 0xfff30000, FMT_D4, {DM, MEM2(D32, SP)}}, -{ "movbu", 0xf440, 0xffc0, FMT_D0, {DM, MEM2(DI, AN)}}, -{ "movbu", 0x020000, 0xf30000, FMT_S2, {DM, MEM(ABS16)}}, -{ "movbu", 0xfc820000, 0xfff30000, FMT_D4, {DM, MEM(ABS32)}}, - -{ "movhu", 0xf060, 0xfff0, FMT_D0, {MEM(AM), DN}}, -{ "movhu", 0xf86000, 0xfff000, FMT_D1, {MEM2(SD8, AM), DN}}, -{ "movhu", 0xfa600000, 0xfff00000, FMT_D2, {MEM2(SD16, AM), DN}}, -{ "movhu", 0xfc600000, 0xfff00000, FMT_D4, {MEM2(D32, AM), DN}}, -{ "movhu", 0xf8bc00, 0xfffc00, FMT_D1, {MEM2(D8, SP), DN}}, -{ "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN}}, -{ "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN}}, -{ "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM), DN}}, -{ "movhu", 0xc80000, 0xfc0000, FMT_S2, {MEM(ABS16), DN}}, -{ "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN}}, -{ "movhu", 0xf070, 0xfff0, FMT_D0, {DM, MEM(AN)}}, -{ "movhu", 0xf87000, 0xfff000, FMT_D1, {DM, MEM2(SD8, AN)}}, -{ "movhu", 0xfa700000, 0xfff00000, FMT_D2, {DM, MEM2(SD16, AN)}}, -{ "movhu", 0xfc700000, 0xfff00000, FMT_D4, {DM, MEM2(D32, AN)}}, -{ "movhu", 0xf89300, 0xfff300, FMT_D1, {DM, MEM2(D8, SP)}}, -{ "movhu", 0xfa930000, 0xfff30000, FMT_D2, {DM, MEM2(D16, SP)}}, -{ "movhu", 0xfc930000, 0xfff30000, FMT_D4, {DM, MEM2(D32, SP)}}, -{ "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM, MEM2(DI, AN)}}, -{ "movhu", 0x030000, 0xf30000, FMT_S2, {DM, MEM(ABS16)}}, -{ "movhu", 0xfc830000, 0xfff30000, FMT_D4, {DM, MEM(ABS32)}}, - -{ "ext", 0xf2d0, 0xfffc, FMT_D0, {DN}}, -{ "extb", 0x10, 0xfc, FMT_S0, {DN}}, -{ "extbu", 0x14, 0xfc, FMT_S0, {DN}}, -{ "exth", 0x18, 0xfc, FMT_S0, {DN}}, -{ "exthu", 0x1c, 0xfc, FMT_S0, {DN}}, +{ "mov", 0x8000, 0xf000, FMT_S1, {SIMM8, DN0}}, +{ "mov", 0x80, 0xf0, FMT_S0, {DM1, DN0}}, +{ "mov", 0xf1e0, 0xfff0, FMT_D0, {DM1, AN0}}, +{ "mov", 0xf1d0, 0xfff0, FMT_D0, {AM1, DN0}}, +{ "mov", 0x9000, 0xf000, FMT_S1, {IMM8, AN0}}, +{ "mov", 0x90, 0xf0, FMT_S0, {AM1, AN0}}, +{ "mov", 0x3c, 0xfc, FMT_S0, {SP, AN0}}, +{ "mov", 0xf2f0, 0xfff3, FMT_D0, {AM1, SP}}, +{ "mov", 0xf2e4, 0xfffc, FMT_D0, {PSW, DN0}}, +{ "mov", 0xf2f3, 0xfff3, FMT_D0, {DM1, PSW}}, +{ "mov", 0xf2e0, 0xfffc, FMT_D0, {MDR, DN0}}, +{ "mov", 0xf2f2, 0xfff3, FMT_D0, {DM1, MDR}}, +{ "mov", 0x70, 0xf0, FMT_S0, {MEM(AM0), DN1}}, +{ "mov", 0xf80000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}}, +{ "mov", 0xfa000000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}}, +{ "mov", 0xfc000000, 0xfff00000, FMT_D4, {MEM2(D32, AM0), DN1}}, +{ "mov", 0x5800, 0xfc00, FMT_S1, {MEM2(D8, SP), DN0}}, +{ "mov", 0xfab40000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN0}}, +{ "mov", 0xfcb40000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN0}}, +{ "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN0}}, +{ "mov", 0x300000, 0xfc0000, FMT_S2, {MEM(ABS16), DN0}}, +{ "mov", 0xfca40000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN0}}, +{ "mov", 0xf000, 0xfff0, FMT_D0, {MEM(AM0), AN1}}, +{ "mov", 0xf82000, 0xfff000, FMT_D1, {MEM2(D8, AM0), AN1}}, +{ "mov", 0xfa200000, 0xfff00000, FMT_D2, {MEM2(D16, AM0), AN1}}, +{ "mov", 0xfc200000, 0xfff00000, FMT_D4, {MEM2(D32, AM0), AN1}}, +{ "mov", 0x5c00, 0xfc00, FMT_S1, {MEM2(D8, SP), AN0}}, +{ "mov", 0xfab00000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), AN0}}, +{ "mov", 0xfcb00000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), AN0}}, +{ "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM0), AN0}}, +{ "mov", 0xfaa00000, 0xfffc0000, FMT_D2, {MEM(ABS16), AN0}}, +{ "mov", 0xfca00000, 0xfffc0000, FMT_D4, {MEM(ABS32), AN0}}, +{ "mov", 0xf8f000, 0xfffc00, FMT_D1, {MEM2(SD8N, AM0), SP}}, +{ "mov", 0x60, 0xf0, FMT_S0, {DM1, MEM(AN0)}}, +{ "mov", 0xf81000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}}, +{ "mov", 0xfa100000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}}, +{ "mov", 0xfc100000, 0xfff00000, FMT_D4, {DM1, MEM2(D32, AN0)}}, +{ "mov", 0x4200, 0xf300, FMT_S1, {DM1, MEM2(D8, SP)}}, +{ "mov", 0xfa910000, 0xfff30000, FMT_D2, {DM1, MEM2(D16, SP)}}, +{ "mov", 0xfc910000, 0xfff30000, FMT_D4, {DM1, MEM2(D32, SP)}}, +{ "mov", 0xf340, 0xffc0, FMT_D0, {DM0, MEM2(DI, AN0)}}, +{ "mov", 0x010000, 0xf30000, FMT_S2, {DM1, MEM(ABS16)}}, +{ "mov", 0xfc810000, 0xfff30000, FMT_D4, {DM1, MEM(ABS32)}}, +{ "mov", 0xf010, 0xfff0, FMT_D0, {AM1, MEM(AN0)}}, +{ "mov", 0xf83000, 0xfff000, FMT_D1, {AM1, MEM2(SD8, AN0)}}, +{ "mov", 0xfa300000, 0xfff00000, FMT_D2, {AM1, MEM2(SD16, AN0)}}, +{ "mov", 0xfc300000, 0xfff00000, FMT_D4, {AM1, MEM2(D32, AN0)}}, +{ "mov", 0x4300, 0xf300, FMT_S1, {AM1, MEM2(D8, SP)}}, +{ "mov", 0xfa900000, 0xfff30000, FMT_D2, {AM1, MEM2(D16, SP)}}, +{ "mov", 0xfc900000, 0xfc930000, FMT_D4, {AM1, MEM2(D32, SP)}}, +{ "mov", 0xf3c0, 0xffc0, FMT_D0, {AM0, MEM2(DI, AN0)}}, +{ "mov", 0xfa800000, 0xfff30000, FMT_D2, {AM1, MEM(ABS16)}}, +{ "mov", 0xfc800000, 0xfff30000, FMT_D4, {AM1, MEM(ABS32)}}, +{ "mov", 0xf8f400, 0xfffc00, FMT_D1, {SP, MEM2(SD8N, AN0)}}, +{ "mov", 0x2c0000, 0xfc0000, FMT_S2, {SIMM16, DN0}}, +{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, +{ "mov", 0x240000, 0xfc0000, FMT_S2, {IMM16, AN0}}, +{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, AN0}}, + +{ "movbu", 0xf040, 0xfff0, FMT_D0, {MEM(AM0), DN1}}, +{ "movbu", 0xf84000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}}, +{ "movbu", 0xfa400000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}}, +{ "movbu", 0xfc400000, 0xfff00000, FMT_D4, {MEM2(D32, AM0), DN1}}, +{ "movbu", 0xf8b800, 0xfffc00, FMT_D1, {MEM2(D8, SP), DN0}}, +{ "movbu", 0xfab80000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN0}}, +{ "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN0}}, +{ "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN0}}, +{ "movbu", 0x340000, 0xfc0000, FMT_S2, {MEM(ABS16), DN0}}, +{ "movbu", 0xfca80000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN0}}, +{ "movbu", 0xf050, 0xfff0, FMT_D0, {DM1, MEM(AN0)}}, +{ "movbu", 0xf85000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}}, +{ "movbu", 0xfa500000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}}, +{ "movbu", 0xfc500000, 0xfff00000, FMT_D4, {DM1, MEM2(D32, AN0)}}, +{ "movbu", 0xf89200, 0xfff300, FMT_D1, {DM1, MEM2(D8, SP)}}, +{ "movbu", 0xfa920000, 0xfff30000, FMT_D2, {DM1, MEM2(D16, SP)}}, +{ "movbu", 0xfc920000, 0xfff30000, FMT_D4, {DM1, MEM2(D32, SP)}}, +{ "movbu", 0xf440, 0xffc0, FMT_D0, {DM0, MEM2(DI, AN0)}}, +{ "movbu", 0x020000, 0xf30000, FMT_S2, {DM1, MEM(ABS16)}}, +{ "movbu", 0xfc820000, 0xfff30000, FMT_D4, {DM1, MEM(ABS32)}}, + +{ "movhu", 0xf060, 0xfff0, FMT_D0, {MEM(AM0), DN1}}, +{ "movhu", 0xf86000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}}, +{ "movhu", 0xfa600000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}}, +{ "movhu", 0xfc600000, 0xfff00000, FMT_D4, {MEM2(D32, AM0), DN1}}, +{ "movhu", 0xf8bc00, 0xfffc00, FMT_D1, {MEM2(D8, SP), DN0}}, +{ "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN0}}, +{ "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN0}}, +{ "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN0}}, +{ "movhu", 0xc80000, 0xfc0000, FMT_S2, {MEM(ABS16), DN0}}, +{ "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN0}}, +{ "movhu", 0xf070, 0xfff0, FMT_D0, {DM1, MEM(AN0)}}, +{ "movhu", 0xf87000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}}, +{ "movhu", 0xfa700000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}}, +{ "movhu", 0xfc700000, 0xfff00000, FMT_D4, {DM1, MEM2(D32, AN0)}}, +{ "movhu", 0xf89300, 0xfff300, FMT_D1, {DM1, MEM2(D8, SP)}}, +{ "movhu", 0xfa930000, 0xfff30000, FMT_D2, {DM1, MEM2(D16, SP)}}, +{ "movhu", 0xfc930000, 0xfff30000, FMT_D4, {DM1, MEM2(D32, SP)}}, +{ "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM0, MEM2(DI, AN0)}}, +{ "movhu", 0x030000, 0xf30000, FMT_S2, {DM1, MEM(ABS16)}}, +{ "movhu", 0xfc830000, 0xfff30000, FMT_D4, {DM1, MEM(ABS32)}}, + +{ "ext", 0xf2d0, 0xfffc, FMT_D0, {DN0}}, +{ "extb", 0x10, 0xfc, FMT_S0, {DN0}}, +{ "extbu", 0x14, 0xfc, FMT_S0, {DN0}}, +{ "exth", 0x18, 0xfc, FMT_S0, {DN0}}, +{ "exthu", 0x1c, 0xfc, FMT_S0, {DN0}}, { "movm", 0xce00, 0xff00, FMT_S1, {MEM(SP), IMM8}}, { "movm", 0xcf00, 0xff00, FMT_S1, {IMM8, MEM(SP)}}, -{ "clr", 0x00, 0xf3, FMT_S0, {DN}}, - -{ "add", 0xe0, 0xf0, FMT_S0, {DM, DN}}, -{ "add", 0xf160, 0xfff0, FMT_D0, {DM, AN}}, -{ "add", 0xf150, 0xfff0, FMT_D0, {AM, DN}}, -{ "add", 0xf170, 0xfff0, FMT_D0, {AM, AN}}, -{ "add", 0x2800, 0xfc00, FMT_S1, {SIMM8, DN}}, -{ "add", 0xfac00000, 0xfffc0000, FMT_D2, {SIMM16, DN}}, -{ "add", 0xfcc00000, 0xfffc0000, FMT_D4, {IMM32, DN}}, -{ "add", 0x2000, 0xfc00, FMT_S1, {SIMM8, AN}}, -{ "add", 0xfad00000, 0xfffc0000, FMT_D2, {SIMM16, AN}}, -{ "add", 0xfcd00000, 0xfffc0000, FMT_D4, {IMM32, AN}}, +{ "clr", 0x00, 0xf3, FMT_S0, {DN1}}, + +{ "add", 0xe0, 0xf0, FMT_S0, {DM1, DN0}}, +{ "add", 0xf160, 0xfff0, FMT_D0, {DM1, AN0}}, +{ "add", 0xf150, 0xfff0, FMT_D0, {AM1, DN0}}, +{ "add", 0xf170, 0xfff0, FMT_D0, {AM1, AN0}}, +{ "add", 0x2800, 0xfc00, FMT_S1, {SIMM8, DN0}}, +{ "add", 0xfac00000, 0xfffc0000, FMT_D2, {SIMM16, DN0}}, +{ "add", 0xfcc00000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, +{ "add", 0x2000, 0xfc00, FMT_S1, {SIMM8, AN0}}, +{ "add", 0xfad00000, 0xfffc0000, FMT_D2, {SIMM16, AN0}}, +{ "add", 0xfcd00000, 0xfffc0000, FMT_D4, {IMM32, AN0}}, { "add", 0xf8fe00, 0xffff00, FMT_D1, {SIMM8, SP}}, { "add", 0xfafe0000, 0xfffc0000, FMT_D2, {SIMM16, SP}}, { "add", 0xfcfe0000, 0xfff0000, FMT_D4, {IMM32, SP}}, -{ "addc", 0xf140, 0xfff0, FMT_D0, {DM, DN}}, - -{ "sub", 0xf100, 0xfff0, FMT_D0, {DM, DN}}, -{ "sub", 0xf120, 0xfff0, FMT_D0, {DM, AN}}, -{ "sub", 0xf110, 0xfff0, FMT_D0, {AM, DN}}, -{ "sub", 0xf130, 0xfff0, FMT_D0, {AM, AN}}, -{ "sub", 0xfcc40000, 0xfffc0000, FMT_D4, {IMM32, DN}}, -{ "sub", 0xfcd40000, 0xfffc0000, FMT_D4, {IMM32, AN}}, -{ "subc", 0xf180, 0xfff0, FMT_D0, {DM, DN}}, - -{ "mul", 0xf240, 0xfff0, FMT_D0, {DM, DN}}, -{ "mulu", 0xf250, 0xfff0, FMT_D0, {DM, DN}}, - -{ "div", 0xf260, 0xfff0, FMT_D0, {DM, DN}}, -{ "divu", 0xf270, 0xfff0, FMT_D0, {DM, DN}}, - -{ "inc", 0x40, 0xf3, FMT_S0, {DN}}, -{ "inc", 0x41, 0xf3, FMT_S0, {AN}}, -{ "inc4", 0x50, 0xfc, FMT_S0, {AN}}, - -{ "cmp", 0xa000, 0xf000, FMT_S1, {SIMM8, DN}}, -{ "cmp", 0xa0, 0xf0, FMT_S0, {DM, DN}}, -{ "cmp", 0xf1a0, 0xfff0, FMT_D0, {DM, AN}}, -{ "cmp", 0xf190, 0xfff0, FMT_D0, {AM, DN}}, -{ "cmp", 0xb000, 0xf000, FMT_S1, {IMM8, AN}}, -{ "cmp", 0xb0, 0xf0, FMT_S0, {AM, AN}}, -{ "cmp", 0xfac80000, 0xfffc0000, FMT_D2, {SIMM16, DN}}, -{ "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, {IMM32, DN}}, -{ "cmp", 0xfad80000, 0xfffc0000, FMT_D2, {IMM16, AN}}, -{ "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, {IMM32, AN}}, - -{ "and", 0xf200, 0xfff0, FMT_D0, {DM, DN}}, -{ "and", 0xf8e000, 0xfffc00, FMT_D1, {IMM8, DN}}, -{ "and", 0xfae00000, 0xfffc0000, FMT_D2, {IMM16, DN}}, -{ "and", 0xfce00000, 0xfffc0000, FMT_D4, {IMM32, DN}}, +{ "addc", 0xf140, 0xfff0, FMT_D0, {DM1, DN0}}, + +{ "sub", 0xf100, 0xfff0, FMT_D0, {DM1, DN0}}, +{ "sub", 0xf120, 0xfff0, FMT_D0, {DM1, AN0}}, +{ "sub", 0xf110, 0xfff0, FMT_D0, {AM1, DN0}}, +{ "sub", 0xf130, 0xfff0, FMT_D0, {AM1, AN0}}, +{ "sub", 0xfcc40000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, +{ "sub", 0xfcd40000, 0xfffc0000, FMT_D4, {IMM32, AN0}}, +{ "subc", 0xf180, 0xfff0, FMT_D0, {DM1, DN0}}, + +{ "mul", 0xf240, 0xfff0, FMT_D0, {DM1, DN0}}, +{ "mulu", 0xf250, 0xfff0, FMT_D0, {DM1, DN0}}, + +{ "div", 0xf260, 0xfff0, FMT_D0, {DM1, DN0}}, +{ "divu", 0xf270, 0xfff0, FMT_D0, {DM1, DN0}}, + +{ "inc", 0x40, 0xf3, FMT_S0, {DN1}}, +{ "inc", 0x41, 0xf3, FMT_S0, {AN1}}, +{ "inc4", 0x50, 0xfc, FMT_S0, {AN0}}, + +{ "cmp", 0xa000, 0xf000, FMT_S1, {SIMM8, DN0}}, +{ "cmp", 0xa0, 0xf0, FMT_S0, {DM1, DN0}}, +{ "cmp", 0xf1a0, 0xfff0, FMT_D0, {DM1, AN0}}, +{ "cmp", 0xf190, 0xfff0, FMT_D0, {AM1, DN0}}, +{ "cmp", 0xb000, 0xf000, FMT_S1, {IMM8, AN0}}, +{ "cmp", 0xb0, 0xf0, FMT_S0, {AM1, AN0}}, +{ "cmp", 0xfac80000, 0xfffc0000, FMT_D2, {SIMM16, DN0}}, +{ "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, +{ "cmp", 0xfad80000, 0xfffc0000, FMT_D2, {IMM16, AN0}}, +{ "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, {IMM32, AN0}}, + +{ "and", 0xf200, 0xfff0, FMT_D0, {DM1, DN0}}, +{ "and", 0xf8e000, 0xfffc00, FMT_D1, {IMM8, DN0}}, +{ "and", 0xfae00000, 0xfffc0000, FMT_D2, {IMM16, DN0}}, +{ "and", 0xfce00000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, { "and", 0xfafc0000, 0xfffc0000, FMT_D2, {IMM16, PSW}}, -{ "or", 0xf210, 0xfff0, FMT_D0, {DM, DN}}, -{ "or", 0xf8e400, 0xfffc00, FMT_D1, {IMM8, DN}}, -{ "or", 0xfae40000, 0xfffc0000, FMT_D2, {IMM16, DN}}, -{ "or", 0xfce40000, 0xfffc0000, FMT_D4, {IMM32, DN}}, +{ "or", 0xf210, 0xfff0, FMT_D0, {DM1, DN0}}, +{ "or", 0xf8e400, 0xfffc00, FMT_D1, {IMM8, DN0}}, +{ "or", 0xfae40000, 0xfffc0000, FMT_D2, {IMM16, DN0}}, +{ "or", 0xfce40000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, { "or", 0xfafd0000, 0xfffc0000, FMT_D2, {IMM16, PSW}}, -{ "xor", 0xf220, 0xfff0, FMT_D0, {DM, DN}}, -{ "xor", 0xfae80000, 0xfffc0000, FMT_D2, {IMM16, DN}}, -{ "xor", 0xfce80000, 0xfffc0000, FMT_D4, {IMM32, DN}}, -{ "not", 0xf230, 0xfffc, FMT_D0, {DN}}, - -{ "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN}}, -{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN}}, -{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN}}, +{ "xor", 0xf220, 0xfff0, FMT_D0, {DM1, DN0}}, +{ "xor", 0xfae80000, 0xfffc0000, FMT_D2, {IMM16, DN0}}, +{ "xor", 0xfce80000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, +{ "not", 0xf230, 0xfffc, FMT_D0, {DN0}}, + +{ "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN0}}, +{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}}, +{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, { "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}}, -{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N, AN)}}, -{ "bset", 0xf080, 0xfff0, FMT_D0, {DM, MEM(AN)}}, +{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N,AN0)}}, +{ "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}}, { "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}}, -{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N, AN)}}, -{ "bclr", 0xf090, 0xfff0, FMT_D0, {DM, MEM(AN)}}, +{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N,AN0)}}, +{ "bclr", 0xf090, 0xfff0, FMT_D0, {DM1, MEM(AN0)}}, { "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}}, -{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N, AN)}}, - -{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM, DN}}, -{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN}}, -{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM, DN}}, -{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN}}, -{ "asl", 0xf290, 0xfff0, FMT_D0, {DM, DN}}, -{ "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN}}, -{ "asl2", 0x54, 0xfc, FMT_S0, {DN}}, -{ "ror", 0xf284, 0xfffc, FMT_D0, {DN}}, -{ "rol", 0xf280, 0xfffc, FMT_D0, {DN}}, +{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N,AN0)}}, + +{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN1}}, +{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}}, +{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN1}}, +{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}}, +{ "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN1}}, +{ "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN0}}, +{ "asl2", 0x54, 0xfc, FMT_S0, {DN0}}, +{ "ror", 0xf284, 0xfffc, FMT_D0, {DN0}}, +{ "rol", 0xf280, 0xfffc, FMT_D0, {DN0}}, { "beq", 0xc800, 0xff00, FMT_S1, {SD8N}}, { "bne", 0xc900, 0xff00, FMT_S1, {SD8N}}, @@ -349,12 +361,12 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}}, { "setlb", 0xdb, 0xff, FMT_S0, {UNUSED}}, -{ "jmp", 0xf0f4, 0xfffc, FMT_D0, {AN}}, +{ "jmp", 0xf0f4, 0xfffc, FMT_D0, {AN0}}, { "jmp", 0xcc0000, 0xff0000, FMT_S2, {D16}}, { "jmp", 0xdc0000, 0xff0000, FMT_S4, {D32}}, { "call", 0xcd000000, 0xff000000, FMT_S4, {D16,IMM8,IMM8}}, { "call", 0xdd000000, 0xff000000, FMT_S6, {D32,IMM8,IMM8}}, -{ "calls", 0xf0f0, 0xfffc, FMT_D0, {AN}}, +{ "calls", 0xf0f0, 0xfffc, FMT_D0, {AN0}}, { "calls", 0xfaff0000, 0xffff0000, FMT_D2, {D16}}, { "calls", 0xfcff0000, 0xffff0000, FMT_D4, {D32}}, @@ -367,19 +379,19 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "nop", 0xcb, 0xff, FMT_S0, {UNUSED}}, /* { "udf", 0, 0, {0}}, */ -{ "putx", 0xf500, 0xfff0, FMT_D0, {DM}}, -{ "getx", 0xf6f0, 0xfff0, FMT_D0, {DN}}, -{ "mulq", 0xf600, 0xfff0, FMT_D0, {DM, DN}}, -{ "mulq", 0xf90000, 0xfffc00, FMT_D1, {SIMM8, DN}}, -{ "mulq", 0xfb000000, 0xfffc0000, FMT_D2, {SIMM16, DN}}, -{ "mulq", 0xfd000000, 0xfffc0000, FMT_D4, {IMM32, DN}}, -{ "mulqu", 0xf610, 0xfff0, FMT_D0, {DM, DN}}, -{ "mulqu", 0xf90400, 0xfffc00, FMT_D1, {SIMM8, DN}}, -{ "mulqu", 0xfb040000, 0xfffc0000, FMT_D2, {SIMM16, DN}}, -{ "mulqu", 0xfd040000, 0xfffc0000, FMT_D4, {IMM32, DN}}, -{ "sat16", 0xf640, 0xfff0, FMT_D0, {DM, DN}}, -{ "sat24", 0xf650, 0xfff0, FMT_D0, {DM, DN}}, -{ "bsch", 0xf670, 0xfff0, FMT_D0, {DM, DN}}, +{ "putx", 0xf500, 0xfff0, FMT_D0, {DM0}}, +{ "getx", 0xf6f0, 0xfff0, FMT_D0, {DN0}}, +{ "mulq", 0xf600, 0xfff0, FMT_D0, {DM1, DN0}}, +{ "mulq", 0xf90000, 0xfffc00, FMT_D1, {SIMM8, DN0}}, +{ "mulq", 0xfb000000, 0xfffc0000, FMT_D2, {SIMM16, DN0}}, +{ "mulq", 0xfd000000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, +{ "mulqu", 0xf610, 0xfff0, FMT_D0, {DM1, DN0}}, +{ "mulqu", 0xf90400, 0xfffc00, FMT_D1, {SIMM8, DN0}}, +{ "mulqu", 0xfb040000, 0xfffc0000, FMT_D2, {SIMM16, DN0}}, +{ "mulqu", 0xfd040000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, +{ "sat16", 0xf640, 0xfff0, FMT_D0, {DM1, DN0}}, +{ "sat24", 0xf650, 0xfff0, FMT_D0, {DM1, DN0}}, +{ "bsch", 0xf670, 0xfff0, FMT_D0, {DM1, DN0}}, { 0, 0, 0, 0, {0}}, } ; -- 2.30.2