From 36d68ce1d30026f8ded0af27366136b6f258fc17 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 14:30:44 +0100 Subject: [PATCH] test against Logical (hard-coded change) --- src/soc/simple/test/test_core.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 8063b97b..6a3f5cb2 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -12,8 +12,9 @@ from soc.decoder.power_enums import Function from soc.simple.core import NonProductionCore from soc.experiment.compalu_multi import find_ok # hack -# test with ALU data -from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase, test_data +# test with ALU data and Logical data +#from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase, test_data +from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, test_data def set_cu_input(cu, idx, data): @@ -106,9 +107,9 @@ def get_inp_indexed(cu, inp): class TestRunner(FHDLTestCase): - def __init__(self, test_data): + def __init__(self, tst_data): super().__init__("run_all") - self.test_data = test_data + self.test_data = tst_data def run_all(self): m = Module() -- 2.30.2