From 36d9d78c5efde823a2597763df91780485931062 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 8 Aug 2019 16:02:34 +0200 Subject: [PATCH] build/altera/common: improve presentation --- litex/build/altera/common.py | 44 +++++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 16 deletions(-) diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py index 7134b6e5..288e7184 100644 --- a/litex/build/altera/common.py +++ b/litex/build/altera/common.py @@ -12,11 +12,14 @@ from migen.fhdl.structure import * class AlteraDifferentialInputImpl(Module): def __init__(self, i_p, i_n, o): - self.specials += Instance("ALT_INBUF_DIFF", - name="ibuf_diff", - i_i=i_p, - i_ibar=i_n, - o_o=o) + self.specials += [ + Instance("ALT_INBUF_DIFF", + name="ibuf_diff", + i_i=i_p, + i_ibar=i_n, + o_o=o + ) + ] class AlteraDifferentialInput: @@ -27,11 +30,14 @@ class AlteraDifferentialInput: class AlteraDifferentialOutputImpl(Module): def __init__(self, i, o_p, o_n): - self.specials += Instance("ALT_OUTBUF_DIFF", - name="obuf_diff", - i_i=i, - o_o=o_p, - o_obar=o_n) + self.specials += [ + Instance("ALT_OUTBUF_DIFF", + name="obuf_diff", + i_i=i, + o_o=o_p, + o_obar=o_n + ) + ] class AlteraDifferentialOutput: @@ -39,6 +45,7 @@ class AlteraDifferentialOutput: def lower(dr): return AlteraDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n) + class AlteraAsyncResetSynchronizerImpl(Module): def __init__(self, cd, async_reset): if not hasattr(async_reset, "attr"): @@ -46,14 +53,19 @@ class AlteraAsyncResetSynchronizerImpl(Module): self.comb += async_reset.eq(i) rst_meta = Signal() self.specials += [ - Instance("DFF", i_d=0, i_clk=cd.clk, i_clrn=1, - i_prn=async_reset, o_q=rst_meta, - attr={"async_reg", "ars_ff1"}), - Instance("DFF", i_d=rst_meta, i_clk=cd.clk, i_clrn=1, - i_prn=async_reset, o_q=cd.rst, - attr={"async_reg", "ars_ff2"}) + Instance("DFF", + i_d=0, i_clk=cd.clk, i_clrn=1, + i_prn=async_reset, o_q=rst_meta, + attr={"async_reg", "ars_ff1"} + ), + Instance("DFF", + i_d=rst_meta, i_clk=cd.clk, i_clrn=1, + i_prn=async_reset, o_q=cd.rst, + attr={"async_reg", "ars_ff2"} + ) ] + class AlteraAsyncResetSynchronizer: @staticmethod def lower(dr): -- 2.30.2