From 370c8b5ee7666f4f515d63603afe8282b1b3c682 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 24 Feb 2012 16:36:05 +0100 Subject: [PATCH] r600g: remove obsolete todo comments MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Also use XXX in the other ones, because it's the most used word for that purpose in Mesa. Reviewed-by: Alex Deucher Reviewed-by: Christian König --- src/gallium/drivers/r600/eg_sq.h | 2 +- src/gallium/drivers/r600/evergreen_state.c | 11 ++++------- src/gallium/drivers/r600/r600_asm.c | 2 +- src/gallium/drivers/r600/r600_blit.c | 2 +- src/gallium/drivers/r600/r600_pipe.c | 14 +++++++------- src/gallium/drivers/r600/r600_shader.c | 10 +++++----- src/gallium/drivers/r600/r600_state.c | 5 +---- src/gallium/drivers/r600/r600_state_common.c | 2 -- src/gallium/drivers/r600/r600_texture.c | 6 ++---- 9 files changed, 22 insertions(+), 32 deletions(-) diff --git a/src/gallium/drivers/r600/eg_sq.h b/src/gallium/drivers/r600/eg_sq.h index eba42d09a06..b534872f062 100644 --- a/src/gallium/drivers/r600/eg_sq.h +++ b/src/gallium/drivers/r600/eg_sq.h @@ -335,7 +335,7 @@ #define S_SQ_ALU_WORD1_OP3_ALU_INST(x) (((x) & 0x1F) << 13) #define G_SQ_ALU_WORD1_OP3_ALU_INST(x) (((x) >> 13) & 0x1F) #define C_SQ_ALU_WORD1_OP3_ALU_INST 0xFFFC1FFF -/* TODO ADD OTHER OP3 */ +/* XXX ADD OTHER OP3 */ /* done */ #define P_SQ_VTX_WORD0 #define S_SQ_VTX_WORD0_VTX_INST(x) (((x) & 0x1F) << 0) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 81366e56dac..a40f66dbb45 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -21,9 +21,6 @@ * USE OR OTHER DEALINGS IN THE SOFTWARE. */ -/* TODO: - * - fix mask for depth control & cull for query - */ #include #include #include "pipe/p_defines.h" @@ -636,7 +633,7 @@ static void *evergreen_create_blend_state(struct pipe_context *ctx, struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend); struct r600_pipe_state *rstate; uint32_t color_control, target_mask; - /* FIXME there is more then 8 framebuffer */ + /* XXX there is more then 8 framebuffer */ unsigned blend_cntl[8]; if (blend == NULL) { @@ -1407,7 +1404,7 @@ static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rsta * - 11-bit or smaller UNORM/SNORM/SRGB * - 16-bit or smaller FLOAT */ - /* FIXME: This should probably be the same for all CBs if we want + /* XXX: This should probably be the same for all CBs if we want * useful alpha tests. */ if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && ((desc->channel[i].size < 12 && @@ -1426,7 +1423,7 @@ static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rsta offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture); offset >>= 8; - /* FIXME handle enabling of CB beyond BASE8 which has different offset */ + /* XXX handle enabling of CB beyond BASE8 which has different offset */ r600_pipe_state_add_reg(rstate, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset, &rtex->resource, RADEON_USAGE_READWRITE); @@ -2410,7 +2407,7 @@ void evergreen_polygon_offset_update(struct r600_context *rctx) default: return; } - /* FIXME some of those reg can be computed with cso */ + /* XXX some of those reg can be computed with cso */ offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth); r600_pipe_state_add_reg(&state, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c index 567f2048f5c..dc19936744b 100644 --- a/src/gallium/drivers/r600/r600_asm.c +++ b/src/gallium/drivers/r600/r600_asm.c @@ -2546,7 +2546,7 @@ void r600_bytecode_dump(struct r600_bytecode *bc) fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]); fprintf(stderr, "ENDIAN:%d ", vtx->endian); fprintf(stderr, "OFFSET:%d\n", vtx->offset); - /* TODO */ + /* XXX */ id++; fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]); id++; diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index d58abea487f..9ab85c8713f 100644 --- a/src/gallium/drivers/r600/r600_blit.c +++ b/src/gallium/drivers/r600/r600_blit.c @@ -162,7 +162,7 @@ void r600_flush_depth_textures(struct r600_context *rctx) { unsigned int i; - /* FIXME: This handles fragment shader textures only. */ + /* XXX: This handles fragment shader textures only. */ for (i = 0; i < rctx->ps_samplers.n_views; ++i) { struct r600_pipe_sampler_view *view; diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index b422d753078..fe801aba19f 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -445,7 +445,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) /* Render targets. */ case PIPE_CAP_MAX_RENDER_TARGETS: - /* FIXME some r6xx are buggy and can only do 4 */ + /* XXX some r6xx are buggy and can only do 4 */ return 8; /* Timer queries, present when the clock frequency is non zero. */ @@ -497,14 +497,14 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e case PIPE_SHADER_VERTEX: break; case PIPE_SHADER_GEOMETRY: - /* TODO: support and enable geometry programs */ + /* XXX: support and enable geometry programs */ return 0; default: - /* TODO: support tessellation on Evergreen */ + /* XXX: support tessellation on Evergreen */ return 0; } - /* TODO: all these should be fixed, since r600 surely supports much more! */ + /* XXX: all these should be fixed, since r600 surely supports much more! */ switch (param) { case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: @@ -512,7 +512,7 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: return 16384; case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: - return 8; /* FIXME */ + return 8; /* XXX */ case PIPE_SHADER_CAP_MAX_INPUTS: if(shader == PIPE_SHADER_FRAGMENT) return 34; @@ -521,14 +521,14 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e case PIPE_SHADER_CAP_MAX_TEMPS: return 256; /* Max native temporaries. */ case PIPE_SHADER_CAP_MAX_ADDRS: - /* FIXME Isn't this equal to TEMPS? */ + /* XXX Isn't this equal to TEMPS? */ return 1; /* Max native address registers */ case PIPE_SHADER_CAP_MAX_CONSTS: return R600_MAX_CONST_BUFFER_SIZE; case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: return R600_MAX_CONST_BUFFERS-1; case PIPE_SHADER_CAP_MAX_PREDS: - return 0; /* FIXME */ + return 0; /* nothing uses this */ case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: return 1; case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 6d05df6ae28..4cf39f67f42 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -576,7 +576,7 @@ static int evergreen_gpr_count(struct r600_shader_ctx *ctx) ctx->num_interp_gpr += (num_baryc + 1) >> 1; - /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */ + /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */ return ctx->num_interp_gpr; } @@ -1953,7 +1953,7 @@ static int tgsi_rsq(struct r600_shader_ctx *ctx) memset(&alu, 0, sizeof(struct r600_bytecode_alu)); - /* FIXME: + /* XXX: * For state trackers other than OpenGL, we'll want to use * _RECIPSQRT_IEEE instead. */ @@ -4528,7 +4528,7 @@ static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP)); ctx->bc->cf_last->pop_count = pops; - /* TODO work out offset */ + /* XXX work out offset */ return 0; } @@ -4640,7 +4640,7 @@ static int tgsi_endloop(struct r600_shader_ctx *ctx) for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) { ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id; } - /* TODO add LOOPRET support */ + /* XXX add LOOPRET support */ fc_poplevel(ctx); callstack_decrease_current(ctx, FC_LOOP); return 0; @@ -4727,7 +4727,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = { {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2}, {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit}, - /* FIXME: + /* XXX: * For state trackers other than OpenGL, we'll want to use * _RECIP_IEEE instead. */ diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 170d4612704..806d7dd4b35 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -21,9 +21,6 @@ * USE OR OTHER DEALINGS IN THE SOFTWARE. */ -/* TODO: - * - fix mask for depth control & cull for query - */ #include #include #include "pipe/p_defines.h" @@ -610,7 +607,7 @@ void r600_polygon_offset_update(struct r600_context *rctx) default: return; } - /* FIXME some of those reg can be computed with cso */ + /* XXX some of those reg can be computed with cso */ offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth); r600_pipe_state_add_reg(&state, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index ec030de1cec..1df67dde0c1 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -435,7 +435,6 @@ void r600_bind_ps_shader(struct pipe_context *ctx, void *state) { struct r600_context *rctx = (struct r600_context *)ctx; - /* TODO delete old shader */ rctx->ps_shader = (struct r600_pipe_shader *)state; if (state) { r600_inval_shader_cache(rctx); @@ -453,7 +452,6 @@ void r600_bind_vs_shader(struct pipe_context *ctx, void *state) { struct r600_context *rctx = (struct r600_context *)ctx; - /* TODO delete old shader */ rctx->vs_shader = (struct r600_pipe_shader *)state; if (state) { r600_inval_shader_cache(rctx); diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index a5a94d4aee6..26759153276 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -664,8 +664,6 @@ static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); if (surface == NULL) return NULL; - /* XXX no offset */ -/* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/ pipe_reference_init(&surface->base.reference, 1); pipe_resource_reference(&surface->base.texture, texture); surface->base.context = pipe; @@ -1075,7 +1073,7 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen, default: break; } - goto out_unknown; /* TODO */ + goto out_unknown; /* XXX */ case UTIL_FORMAT_COLORSPACE_SRGB: word4 |= S_038010_FORCE_DEGAMMA(1); @@ -1164,7 +1162,7 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen, } } - /* R8G8Bx_SNORM - TODO CxV8U8 */ + /* R8G8Bx_SNORM - XXX CxV8U8 */ /* See whether the components are of the same size. */ for (i = 1; i < desc->nr_channels; i++) { -- 2.30.2