From 37202a5d845dd037f38303cd599e0226f7779670 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 19 Dec 2018 18:18:23 +0000 Subject: [PATCH] minor correction --- updates/003_2018dec04_microarchitecture.mdwn | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/updates/003_2018dec04_microarchitecture.mdwn b/updates/003_2018dec04_microarchitecture.mdwn index 84bb5b0..ea0376c 100644 --- a/updates/003_2018dec04_microarchitecture.mdwn +++ b/updates/003_2018dec04_microarchitecture.mdwn @@ -94,7 +94,9 @@ clear out the ROB: Branch Prediction simply uses this pre-existing logic. The other way in which out-of-order execution can be handled is called scoreboarding, as well as explicit register renaming. These schemes seem to have significant disadvantages and complexities when compared -to Reorder Buffers: +to Reorder Buffers (however, see later updates: the disadvantages are down +to a complete failure of the academic literature to fully comprehend +the design of the CDC 6600): * Explicit Register renaming needs a global register file quite a bit larger than the "actual" one. The Libre RISC-V SoC already has two whopping @@ -160,6 +162,9 @@ concept: * Scoreboarding does not provide a means to do multi-issue (the ROB does: you just put more than one entry per cycle into the buffer) +(*Note: in later updates, we find that, fascinatingly, these things are +just not true.*) + # Next step The project is being run along ethical lines. That in particular means -- 2.30.2