From 3728e15bd64d0d53057484b3b9f8bd22c29bb15e Mon Sep 17 00:00:00 2001 From: whitequark Date: Sat, 3 Aug 2019 23:43:57 +0000 Subject: [PATCH] back.rtlil: actually match shape of left hand side. This comes up in code such as: Array([Signal(1), Signal(8)]).eq(Const(0, 8)) --- nmigen/back/rtlil.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 8956065..6ef0d86 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -572,8 +572,15 @@ class _LHSValueCompiler(_ValueCompiler): raise TypeError # :nocov: def match_shape(self, value, new_bits, new_sign): - assert value.shape() == (new_bits, new_sign) - return self(value) + value_bits, value_sign = value.shape() + if new_bits == value_bits: + return self(value) + elif new_bits < value_bits: + return self(ast.Slice(value, 0, new_bits)) + else: # new_bits > value_bits + # It is legal to assign to constants on LHS in RTLIL; such assignments are ignored. + dummy_bits = new_bits - value_bits + return "{{ {}'{} {} }}".format(dummy_bits, "x" * dummy_bits, self(value)) def on_Signal(self, value): if value not in self.s.driven: -- 2.30.2