From 3766334923e9180c5ed98a97808dda1a2665332d Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Wed, 18 Apr 2018 11:02:51 +0200 Subject: [PATCH] compiler/nir: add lowering for 16-bit flrp And enable it on Intel. v2: - Squash the change to enable it on Intel (Jason) Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir.h | 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + src/intel/compiler/brw_compiler.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index ee766d5238a..92b17275b45 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -2163,6 +2163,7 @@ typedef struct nir_shader_compiler_options { bool lower_fdiv; bool lower_ffma; bool fuse_ffma; + bool lower_flrp16; bool lower_flrp32; /** Lowers flrp when it does not support doubles */ bool lower_flrp64; diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index ddd8d40676f..78e273d0e64 100644 --- a/src/compiler/nir/nir_opt_algebraic.py +++ b/src/compiler/nir/nir_opt_algebraic.py @@ -128,6 +128,7 @@ optimizations = [ (('~flrp', 0.0, a, b), ('fmul', a, b)), (('~flrp', a, b, ('b2f', 'c@1')), ('bcsel', c, b, a), 'options->lower_flrp32'), (('~flrp', a, 0.0, c), ('fadd', ('fmul', ('fneg', a), c), a)), + (('flrp@16', a, b, c), ('fadd', ('fmul', c, ('fsub', b, a)), a), 'options->lower_flrp16'), (('flrp@32', a, b, c), ('fadd', ('fmul', c, ('fsub', b, a)), a), 'options->lower_flrp32'), (('flrp@64', a, b, c), ('fadd', ('fmul', c, ('fsub', b, a)), a), 'options->lower_flrp64'), (('ffloor', a), ('fsub', a, ('ffract', a)), 'options->lower_ffloor'), diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index b588d5be97b..a3a0a393fad 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -33,6 +33,7 @@ .lower_sub = true, \ .lower_fdiv = true, \ .lower_scmp = true, \ + .lower_flrp16 = true, \ .lower_fmod16 = true, \ .lower_fmod32 = true, \ .lower_fmod64 = false, \ -- 2.30.2