From 3781d1fb1aa2c878ea7931a7bcf346c0ea95a619 Mon Sep 17 00:00:00 2001 From: Alex Solomatnikov Date: Fri, 3 Feb 2017 16:41:59 -0800 Subject: [PATCH] Bug fixes: passing OC WB test --- src/main/scala/devices/i2c/I2C.scala | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala index 40102ba..ac4e58a 100644 --- a/src/main/scala/devices/i2c/I2C.scala +++ b/src/main/scala/devices/i2c/I2C.scala @@ -328,7 +328,7 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap { when (load) { receivedData := transmitData } - .otherwise { + .elsewhen (shift) { receivedData := Cat(receivedData, receivedBit) } @@ -453,6 +453,11 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap { //////// Top level //////// + // hack + val nextCmd = Wire(UInt(8.W)) + nextCmd := cmd.asUInt + cmd := (new CommandBundle).fromBits(nextCmd) + when (cmdAck || arbLost) { cmd.start := false.B // clear command bits when done cmd.stop := false.B // or when aribitration lost @@ -461,6 +466,7 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap { } cmd.irqAck := false.B // clear IRQ_ACK bit (essentially 1 cycle pulse b/c it is overwritten by regmap below) + status.receivedAck := receivedAck when (stopCond) { status.busy := false.B } @@ -477,11 +483,6 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap { status.transferInProgress := cmd.read || cmd.write status.irqFlag := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck - // hack - val nextCmd = Wire(UInt(8.W)) - nextCmd := cmd.asUInt - cmd := (new CommandBundle).fromBits(nextCmd) - // Note that these are out of order. regmap( I2CCtrlRegs.prescaler_lo -> Seq(RegField(8, prescaler.lo)), -- 2.30.2