From 37d49885d3652cd509e90c29f3f052b2070e075c Mon Sep 17 00:00:00 2001 From: Andrew Cagney Date: Wed, 25 Feb 1998 15:04:11 +0000 Subject: [PATCH] Test r5900 floating point instructions. --- sim/testsuite/mips64r5900-elf/f-abs.s | 18 ++++++++ sim/testsuite/mips64r5900-elf/f-add.s | 38 +++++++++++++++++ sim/testsuite/mips64r5900-elf/f-cond.s | 57 +++++++++++++++++++++++++ sim/testsuite/mips64r5900-elf/f-cvt.s | 34 +++++++++++++++ sim/testsuite/mips64r5900-elf/f-div.s | 27 ++++++++++++ sim/testsuite/mips64r5900-elf/f-madd.s | 21 +++++++++ sim/testsuite/mips64r5900-elf/f-madda.s | 13 ++++++ sim/testsuite/mips64r5900-elf/f-max.s | 18 ++++++++ sim/testsuite/mips64r5900-elf/f-min.s | 18 ++++++++ sim/testsuite/mips64r5900-elf/f-msub.s | 13 ++++++ sim/testsuite/mips64r5900-elf/f-msuba.s | 13 ++++++ sim/testsuite/mips64r5900-elf/f-mul.s | 12 ++++++ sim/testsuite/mips64r5900-elf/f-mula.s | 12 ++++++ sim/testsuite/mips64r5900-elf/f-neg.s | 11 +++++ sim/testsuite/mips64r5900-elf/f-sqrt.s | 24 +++++++++++ sim/testsuite/mips64r5900-elf/f-sub.s | 12 ++++++ sim/testsuite/mips64r5900-elf/f-suba.s | 13 ++++++ 17 files changed, 354 insertions(+) create mode 100644 sim/testsuite/mips64r5900-elf/f-abs.s create mode 100644 sim/testsuite/mips64r5900-elf/f-add.s create mode 100644 sim/testsuite/mips64r5900-elf/f-cond.s create mode 100644 sim/testsuite/mips64r5900-elf/f-cvt.s create mode 100644 sim/testsuite/mips64r5900-elf/f-div.s create mode 100644 sim/testsuite/mips64r5900-elf/f-madd.s create mode 100644 sim/testsuite/mips64r5900-elf/f-madda.s create mode 100644 sim/testsuite/mips64r5900-elf/f-max.s create mode 100644 sim/testsuite/mips64r5900-elf/f-min.s create mode 100644 sim/testsuite/mips64r5900-elf/f-msub.s create mode 100644 sim/testsuite/mips64r5900-elf/f-msuba.s create mode 100644 sim/testsuite/mips64r5900-elf/f-mul.s create mode 100644 sim/testsuite/mips64r5900-elf/f-mula.s create mode 100644 sim/testsuite/mips64r5900-elf/f-neg.s create mode 100644 sim/testsuite/mips64r5900-elf/f-sqrt.s create mode 100644 sim/testsuite/mips64r5900-elf/f-sub.s create mode 100644 sim/testsuite/mips64r5900-elf/f-suba.s diff --git a/sim/testsuite/mips64r5900-elf/f-abs.s b/sim/testsuite/mips64r5900-elf/f-abs.s new file mode 100644 index 00000000000..289849f8d00 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-abs.s @@ -0,0 +1,18 @@ +.include "t-macros.i" + + start + +test_abs1: + clearfcsr + loadfp $f1 4.0 + abs.s $f2, $f1 + checkfp 0 $f2 4.0 + +test_abs2: + clearfcsr + loadfp $f1 4.0 + neg.s $f1, $f1 + abs.s $f2, $f1 + checkfp 0 $f2 4.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-add.s b/sim/testsuite/mips64r5900-elf/f-add.s new file mode 100644 index 00000000000..caf006f86a8 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-add.s @@ -0,0 +1,38 @@ +.include "t-macros.i" + + start + +test_add1: + clearfcsr + loadfp $f1 4.0 + loadfp $f2 0.1 + add.s $f3, $f2, $f1 + checkfp 0 $f3 4.1 + +test_add2: + clearfcsr + loadfp $f1 , -4.0 + loadfp $f2 8.0 + add.s $f3, $f2, $f1 + checkfp 0 $f3 4.0 + +test_add3: + clearfcsr + loadfpmax $f1 + loadfpmax $f2 + add.s $f3, $f2, $f1 + checkfpmax FCSR_O $f3 + +test_add4: + clearfcsr + loadfpmax $f1 + neg.s $f1, $f1 + loadfpmax $f2 + neg.s $f2, $f2 + add.s $f3, $f2, $f1 + checkfcsr FCSR_O + clearfcsr + neg.s $f3, $f3 + checkfpmax 0 $f3 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-cond.s b/sim/testsuite/mips64r5900-elf/f-cond.s new file mode 100644 index 00000000000..effa8b1f437 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-cond.s @@ -0,0 +1,57 @@ +.include "t-macros.i" + + start + + loadfp $f1 1.0 + loadfp $f2 2.0 + loadfp $f3 3.0 + +test_f1: + clearfcsr + c.f.s $f1, $f1 + checkfcsr 0 + + +test_eq1: + clearfcsr + c.eq.s $f1, $f1 + checkfcsr FCSR_C + +test_eq2: + clearfcsr + c.eq.s $f1, $f2 + checkfcsr 0 + + +test_lt1: + clearfcsr + c.lt.s $f1, $f1 + checkfcsr 0 + +test_lt2: + clearfcsr + c.lt.s $f1, $f2 + checkfcsr FCSR_C + +test_lt3: + clearfcsr + c.lt.s $f3, $f2 + checkfcsr 0 + + +test_le1: + clearfcsr + c.le.s $f1, $f1 + checkfcsr FCSR_C + +test_le2: + clearfcsr + c.le.s $f1, $f2 + checkfcsr FCSR_C + +test_le3: + clearfcsr + c.le.s $f3, $f2 + checkfcsr 0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-cvt.s b/sim/testsuite/mips64r5900-elf/f-cvt.s new file mode 100644 index 00000000000..8853280bb52 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-cvt.s @@ -0,0 +1,34 @@ +.include "t-macros.i" + + start + +test_cvt1: + clearfcsr + loadfp $f1 4.0 + cvt.s.w $f2, $f1 + mfc1 $10, $2 + check10 0 4 + +test_cvt2: + clearfcsr + loadfp $f1 4.0 + neg.s $f1, $f1 + cvt.s.w $f2, $f1 + mfc1 $10, $2 + check10 0 , -4 + +test_cvt3: + clearfcsr + li $4, 4 + mtc1 $4, $4 + cvt.w.s $f3, $f4 + checkfp 0 $f3 4.0 + +test_cvt4: + clearfcsr + li $4, -4 + mtc1 $4, $4 + cvt.w.s $f3, $f4 + checkfp 0 $f3 , -4.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-div.s b/sim/testsuite/mips64r5900-elf/f-div.s new file mode 100644 index 00000000000..dfdd344f0be --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-div.s @@ -0,0 +1,27 @@ +.include "t-macros.i" + + start + +test_div1: + clearfcsr + loadfp $f1 2.0 + loadfp $f2 4.0 + div.s $f3, $f2, $f1 + checkfp 0 $f3 2.0 + + +test_div2: + clearfcsr + loadfp $f1 0.0 + loadfp $f2 0.0 + div.s $f3, $f2, $f1 + checkfpmax FCSR_I $f3 + +test_div3: + clearfcsr + loadfp $f1 0.0 + loadfp $f2 1.0 + div.s $f3, $f2, $f1 + checkfpmax FCSR_D $f3 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-madd.s b/sim/testsuite/mips64r5900-elf/f-madd.s new file mode 100644 index 00000000000..034041d4d20 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-madd.s @@ -0,0 +1,21 @@ +.include "t-macros.i" + + start + +test_madd1: + clearfcsr + loadacc 1.0 + loadfp $f1 2.0 + loadfp $f2 4.0 + madd.s $f3, $f2, $f1 + checkfp 0 $f3 9.0 + +test_madd2: + clearfcsr + loadacc 4.0 + loadfp $f1 2.0 + loadfp $f2 2.0 + madd.s $f3, $f2, $f1 + checkfp 0 $f3 8.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-madda.s b/sim/testsuite/mips64r5900-elf/f-madda.s new file mode 100644 index 00000000000..eee9580183a --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-madda.s @@ -0,0 +1,13 @@ +.include "t-macros.i" + + start + +test_madda1: + clearfcsr + loadacc 8.0 + loadfp $f1 2.0 + loadfp $f2 4.0 + madda.s $f2, $f1 + checkacc 0 16.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-max.s b/sim/testsuite/mips64r5900-elf/f-max.s new file mode 100644 index 00000000000..59c862b2112 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-max.s @@ -0,0 +1,18 @@ +.include "t-macros.i" + + start + + loadfp $f1, 1.0 + loadfp $f2, 2.0 + +test_max1: + clearfcsr + max.s $f3, $f1, $f2 + checkfp 0 $f3 2.0 + +test_max2: + clearfcsr + max.s $f3, $f2, $f1 + checkfp 0 $f3 2.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-min.s b/sim/testsuite/mips64r5900-elf/f-min.s new file mode 100644 index 00000000000..9663e484978 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-min.s @@ -0,0 +1,18 @@ +.include "t-macros.i" + + start + + loadfp $f1, 1.0 + loadfp $f2, 2.0 + +test_min1: + clearfcsr + min.s $f3, $f1, $f2 + checkfp 0 $f3 1.0 + +test_min2: + clearfcsr + min.s $f3, $f2, $f1 + checkfp 0 $f3 1.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-msub.s b/sim/testsuite/mips64r5900-elf/f-msub.s new file mode 100644 index 00000000000..04e3348de47 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-msub.s @@ -0,0 +1,13 @@ +.include "t-macros.i" + + start + +test_msub1: + clearfcsr + loadacc 4.0 + loadfp $f1 1.0 + loadfp $f2 2.0 + msub.s $f3, $f2, $f1 + checkfp 0 $f3 2.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-msuba.s b/sim/testsuite/mips64r5900-elf/f-msuba.s new file mode 100644 index 00000000000..ce2d5a43afa --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-msuba.s @@ -0,0 +1,13 @@ +.include "t-macros.i" + + start + +test_msuba1: + clearfcsr + loadacc 2.0 + loadfp $f1 1.0 + loadfp $f2 2.0 + msuba.s $f2, $f1 + checkacc 0 0.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-mul.s b/sim/testsuite/mips64r5900-elf/f-mul.s new file mode 100644 index 00000000000..d7131dcacc2 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-mul.s @@ -0,0 +1,12 @@ +.include "t-macros.i" + + start + +test_mul1: + clearfcsr + loadfp $f1 2.0 + loadfp $f2 4.0 + mul.s $f3, $f2, $f1 + checkfp 0 $f3 8.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-mula.s b/sim/testsuite/mips64r5900-elf/f-mula.s new file mode 100644 index 00000000000..83bc85eda2e --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-mula.s @@ -0,0 +1,12 @@ +.include "t-macros.i" + + start + +test_mula1: + clearfcsr + loadfp $f1 2.0 + loadfp $f2 4.0 + mula.s $f2, $f1 + checkacc 0 8.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-neg.s b/sim/testsuite/mips64r5900-elf/f-neg.s new file mode 100644 index 00000000000..0757c0e117a --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-neg.s @@ -0,0 +1,11 @@ +.include "t-macros.i" + + start + +test_neg1: + clearfcsr + loadfp $f1 4.0 + neg.s $f3, $f1 + checkfp 0 $f3 , -4.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-sqrt.s b/sim/testsuite/mips64r5900-elf/f-sqrt.s new file mode 100644 index 00000000000..ab7660443d7 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-sqrt.s @@ -0,0 +1,24 @@ +.include "t-macros.i" + + start + +test_sqrt_4_0: + clearfcsr + loadfp $f1 4.0 + sqrt.s $f2, $f1 + checkfp 0 $f2 2.0 + +test_sqrt_0_01: + clearfcsr + loadfp $f1 0.01 + sqrt.s $f2, $f1 + checkfp 0 $f2 0.1 + +test_sqrt_minus_4_0: + clearfcsr + loadfp $f1 4.0 + neg.s $f1, $f1 + sqrt.s $f2, $f1 + checkfp FCSR_I $f2 2.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-sub.s b/sim/testsuite/mips64r5900-elf/f-sub.s new file mode 100644 index 00000000000..59f8898f056 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-sub.s @@ -0,0 +1,12 @@ +.include "t-macros.i" + + start + +test_sub1: + clearfcsr + loadfp $f1 1.0 + loadfp $f2 2.0 + sub.s $f3, $f2, $f1 + checkfp 0 $f3 1.0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/f-suba.s b/sim/testsuite/mips64r5900-elf/f-suba.s new file mode 100644 index 00000000000..abb1f9544a9 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/f-suba.s @@ -0,0 +1,13 @@ +.include "t-macros.i" + + start + +test_suba1: + clearfcsr + loadacc 0.0 + loadfp $f1 1.0 + loadfp $f2 2.0 + suba.s $f2, $f1 + checkacc 0 1.0 + + exit0 -- 2.30.2