From 37ff246f25728fad24a1bd10527676711e72305d Mon Sep 17 00:00:00 2001 From: Adam Greig Date: Thu, 30 Jul 2020 08:05:18 +0100 Subject: [PATCH] hdl.mem: cast reset value for transparent read ports to integer. --- nmigen/hdl/mem.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py index d34c5f0..5b016ab 100644 --- a/nmigen/hdl/mem.py +++ b/nmigen/hdl/mem.py @@ -145,7 +145,7 @@ class ReadPort(Elaboratable): # value of the data output is forcibly set to the 0th initial value, if any--note that # many FPGAs do not guarantee this behavior! if len(self.memory.init) > 0: - self.data.reset = self.memory.init[0] + self.data.reset = operator.index(self.memory.init[0]) latch_addr = Signal.like(self.addr) f.add_statements( latch_addr.eq(self.addr), -- 2.30.2