From 38058776cfe42b83634fe901b8d525a582fa3283 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 29 Mar 2023 17:47:48 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls010.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index 5b6b403e9..9eeb514ff 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -23,7 +23,7 @@ Links: Simple-V is a type of Vectorisation best described as a "Prefix Loop Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR` instruction and to the 8086 `REP` Prefix instruction. More advanced features are similar to the Z80 -`CPIR` instruction. If viewed as an actual Vector ISA it introduces +`CPIR` instruction. If viewed one-dimensionally as an actual Vector ISA it introduces over 1.5 million 64-bit Vector instructions. SVP64, the instruction format, is therefore best viewed as an orthogonal RISC-style "Prefixing" subsystem instead. -- 2.30.2