From 383a72d7f10189c40667c70aa45a1fa93e69b5bc Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 8 Mar 2021 17:00:36 +0000
Subject: [PATCH] add option in TestRunner to disable svp64 via commandline
 test_runner.py nosvp64 currently does nothing

---
 src/soc/simple/issuer_verilog.py   |  8 ++++++++
 src/soc/simple/test/test_issuer.py | 29 ++++++++++++++++++-----------
 src/soc/simple/test/test_runner.py |  5 ++++-
 3 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index f9e65500..a00ec4b1 100644
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -38,6 +38,12 @@ if __name__ == '__main__':
                         default=False)
     parser.add_argument("--debug", default="jtag", help="Select debug " \
                         "interface [jtag | dmi] [default jtag]")
+    parser.add_argument("--enable-svp64", dest='svp64', action="store_true",
+                        help="Enable SVP64",
+                        default=True)
+    parser.add_argument("--disable-svp64", dest='svp64', action="store_false",
+                        help="disable SVP64",
+                        default=False)
 
     args = parser.parse_args()
 
@@ -68,6 +74,7 @@ if __name__ == '__main__':
                          gpio=args.enable_testgpio, # for test purposes
                          sram4x4kblock=args.enable_sram4x4kblock, # add SRAMs
                          debug=args.debug,      # set to jtag or dmi
+                         svp64=args.svp64,      # enable SVP64
                          units=units)
 
     print("nocore", pspec.__dict__["nocore"])
@@ -76,6 +83,7 @@ if __name__ == '__main__':
     print("xics", pspec.__dict__["xics"])
     print("use_pll", pspec.__dict__["use_pll"])
     print("debug", pspec.__dict__["debug"])
+    print("SVP64", pspec.__dict__["svp64"])
 
     dut = TestIssuer(pspec)
 
diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index ebe93b4b..47d112a7 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -9,6 +9,7 @@ related bugs:
 # Also, check out the cxxsim nmigen branch, and latest yosys from git
 
 import unittest
+import sys
 from soc.simple.test.test_runner import TestRunner
 
 # test with ALU data and Logical data
@@ -25,19 +26,25 @@ from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
 
 
 if __name__ == "__main__":
+    svp64 = True
+    if len(sys.argv) == 2:
+        if sys.argv[1] == 'nosvp64':
+            svp64 = False
+        sys.argv.pop()
+
     unittest.main(exit=False)
     suite = unittest.TestSuite()
-    # suite.addTest(TestRunner(HelloTestCases.test_data))
-    suite.addTest(TestRunner(DivTestCases().test_data))
-    # suite.addTest(TestRunner(AttnTestCase.test_data))
-    suite.addTest(TestRunner(GeneralTestCases.test_data))
-    suite.addTest(TestRunner(LDSTTestCase().test_data))
-    suite.addTest(TestRunner(CRTestCase().test_data))
-    suite.addTest(TestRunner(ShiftRotTestCase().test_data))
-    suite.addTest(TestRunner(LogicalTestCase().test_data))
-    suite.addTest(TestRunner(ALUTestCase().test_data))
-    # suite.addTest(TestRunner(BranchTestCase.test_data))
-    # suite.addTest(TestRunner(SPRTestCase.test_data))
+    # suite.addTest(TestRunner(HelloTestCases.test_data, svp64=svp64))
+    suite.addTest(TestRunner(DivTestCases().test_data, svp64=svp64))
+    # suite.addTest(TestRunner(AttnTestCase.test_data, svp64=svp64))
+    suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64))
+    suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64))
+    suite.addTest(TestRunner(CRTestCase().test_data, svp64=svp64))
+    suite.addTest(TestRunner(ShiftRotTestCase().test_data, svp64=svp64))
+    suite.addTest(TestRunner(LogicalTestCase().test_data, svp64=svp64))
+    suite.addTest(TestRunner(ALUTestCase().test_data, svp64=svp64))
+    # suite.addTest(TestRunner(BranchTestCase.test_data, svp64=svp64))
+    # suite.addTest(TestRunner(SPRTestCase.test_data, svp64=svp64))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)
diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 9b8426b6..9e06b8c2 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -121,11 +121,13 @@ def get_dmi(dmi, addr):
 
 
 class TestRunner(FHDLTestCase):
-    def __init__(self, tst_data, microwatt_mmu=False, rom=None):
+    def __init__(self, tst_data, microwatt_mmu=False, rom=None,
+                        svp64=True):
         super().__init__("run_all")
         self.test_data = tst_data
         self.microwatt_mmu = microwatt_mmu
         self.rom = rom
+        self.svp64 = svp64
 
     def run_all(self):
         m = Module()
@@ -143,6 +145,7 @@ class TestRunner(FHDLTestCase):
                              nocore=False,
                              xics=False,
                              gpio=False,
+                             svp64=self.svp64,
                              mmu=self.microwatt_mmu,
                              reg_wid=64)
         m.submodules.issuer = issuer = TestIssuerInternal(pspec)
-- 
2.30.2