From 384b42e2bb5a8a0477e7abca8e46124f7e34a422 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 27 Sep 2018 14:24:48 +0100 Subject: [PATCH] adding sv vector length CSR to processor state, and csr get/set 32 CSRs are used up, here, as SETVL requires not only an immediate but also a target integer register in which the SETVL value is stored. --- riscv/encoding.h | 35 +++++++++++++++++++++++++++++++++++ riscv/processor.cc | 27 +++++++++++++++++++++++++++ riscv/processor.h | 4 ++++ 3 files changed, 66 insertions(+) diff --git a/riscv/encoding.h b/riscv/encoding.h index c109ce1..6ec2564 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -892,6 +892,41 @@ #define CSR_MHPMEVENT29 0x33d #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f +#define CSR_SVGETVL 0xcf0 +#define CSR_SVSETVL_BASE 0x4e0 +#define CSR_SVSETVL_MASK 0x1f +#define CSR_SVSETVL_R0 0x4e0 +#define CSR_SVSETVL_R1 0x4e1 +#define CSR_SVSETVL_R2 0x4e2 +#define CSR_SVSETVL_R3 0x4e3 +#define CSR_SVSETVL_R4 0x4e4 +#define CSR_SVSETVL_R5 0x4e5 +#define CSR_SVSETVL_R6 0x4e6 +#define CSR_SVSETVL_R7 0x4e7 +#define CSR_SVSETVL_R8 0x4e8 +#define CSR_SVSETVL_R9 0x4e9 +#define CSR_SVSETVL_R10 0x4ea +#define CSR_SVSETVL_R11 0x4eb +#define CSR_SVSETVL_R12 0x4ec +#define CSR_SVSETVL_R13 0x4ed +#define CSR_SVSETVL_R14 0x4ee +#define CSR_SVSETVL_R15 0x4ef +#define CSR_SVSETVL_R16 0x4f0 +#define CSR_SVSETVL_R17 0x4f1 +#define CSR_SVSETVL_R18 0x4f2 +#define CSR_SVSETVL_R19 0x4f3 +#define CSR_SVSETVL_R20 0x4f4 +#define CSR_SVSETVL_R21 0x4f5 +#define CSR_SVSETVL_R22 0x4f6 +#define CSR_SVSETVL_R23 0x4f7 +#define CSR_SVSETVL_R24 0x4f8 +#define CSR_SVSETVL_R25 0x4f9 +#define CSR_SVSETVL_R26 0x4fa +#define CSR_SVSETVL_R27 0x4fb +#define CSR_SVSETVL_R28 0x4fc +#define CSR_SVSETVL_R29 0x4fd +#define CSR_SVSETVL_R30 0x4fe +#define CSR_SVSETVL_R31 0x4ff #define CSR_MVENDORID 0xf11 #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 diff --git a/riscv/processor.cc b/riscv/processor.cc index 4a7d0ec..237eedc 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -333,8 +333,31 @@ void processor_t::set_csr(int which, reg_t val) reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | ((ext != NULL) << IRQ_COP); reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP; +#ifdef SPIKE_SIMPLEV + // SV SETVL includes the target register in the lower bits (0-31) + uint64_t sv_target = 0; + uint64_t sv_which = which & ~CSR_SVSETVL_MASK; + if (sv_which == CSR_SVSETVL_BASE) + { + sv_target = which & CSR_SVSETVL_MASK; + which = sv_which; + } +#endif switch (which) { +#ifdef SPIKE_SIMPLEV + case CSR_SVSETVL_BASE: + val = std::min((uint64_t)63, + std::min((uint64_t)val, + state.XPR[sv_target])); + // use CSR_SVSETVL_R0 to set VL to zero without side-effects + if (sv_target != 0) + { + state.XPR.write(sv_target, val); + } + state.vl = val; + break; +#endif case CSR_FFLAGS: dirty_fp_state; state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT); @@ -558,6 +581,10 @@ reg_t processor_t::get_csr(int which) switch (which) { +#ifdef SPIKE_SIMPLEV + case CSR_SVGETV: + return state.vl; +#endif case CSR_FFLAGS: require_fp; if (!supports_extension('F')) diff --git a/riscv/processor.h b/riscv/processor.h index fd90ce3..13466c6 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -123,6 +123,10 @@ struct state_t mcontrol_t mcontrol[num_triggers]; reg_t tdata2[num_triggers]; +#ifdef SPIKE_SIMPLEV + uint64_t vl; +#endif + uint32_t fflags; uint32_t frm; bool serialized; // whether timer CSRs are in a well-defined state -- 2.30.2