From 38847a55cae765e5481cec8dd6d435486fa389a2 Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Sat, 6 Feb 2021 17:17:00 +0530 Subject: [PATCH] arch-power: Refactor load-store instructions This changes the base classes for load-store instructions and introduces two new classes for DS form instructions which use a shifted signed immediate field as the offset from the base address and for X form instructions which use registers for both the offset and the base address. The formats have also been updated to make use of the new base classes. Change-Id: Ib5d1bb5d7747813e0e5b1e3075489f1a3aa72660 Signed-off-by: Sandipan Das --- src/arch/power/insts/mem.hh | 32 ++++++++++++++++++++++++++++++ src/arch/power/isa/decoder.isa | 6 ++---- src/arch/power/isa/formats/mem.isa | 18 +++++++++++++---- 3 files changed, 48 insertions(+), 8 deletions(-) diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh index de9b46cdb..d14f1e6f7 100644 --- a/src/arch/power/insts/mem.hh +++ b/src/arch/power/insts/mem.hh @@ -75,6 +75,38 @@ class MemDispOp : public MemOp Addr pc, const Loader::SymbolTable *symtab) const override; }; +/** + * Class for memory operations with shifted displacement. + */ +class MemDispShiftOp : public MemOp +{ + protected: + + int16_t disp; + + /// Constructor + MemDispShiftOp(const char *mnem, MachInst _machInst, OpClass __opClass) + : MemOp(mnem, _machInst, __opClass), + disp(sext<14>(machInst.ds)) + { + } +}; + + +/** + * Class for memory operations with register indexed addressing. + */ +class MemIndexOp : public MemOp +{ + protected: + + /// Constructor + MemIndexOp(const char *mnem, MachInst _machInst, OpClass __opClass) + : MemOp(mnem, _machInst, __opClass) + { + } +}; + } // namespace PowerISA #endif //__ARCH_POWER_INSTS_MEM_HH__ diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 4005da8d6..b9fc81167 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -132,10 +132,8 @@ decode PO default Unknown::unknown() { } 58: decode DS_XO { - format LoadDispOp { - 2: lwa({{ Rt = Mem_sw; }}, - {{ EA = Ra + (disp & 0xfffffffc); }}, - {{ EA = disp & 0xfffffffc; }}); + format LoadDispShiftOp { + 2: lwa({{ Rt = Mem_sw; }}); } } diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa index c7be2b10d..1f6257143 100644 --- a/src/arch/power/isa/formats/mem.isa +++ b/src/arch/power/isa/formats/mem.isa @@ -240,7 +240,7 @@ def format LoadIndexOp(memacc_code, ea_code = {{ EA = Ra + Rb; }}, mem_flags = [], inst_flags = []) {{ (header_output, decoder_output, decode_block, exec_output) = \ GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, - 'MemOp', 'Load', mem_flags, inst_flags) + 'MemIndexOp', 'Load', mem_flags, inst_flags) }}; @@ -249,7 +249,7 @@ def format StoreIndexOp(memacc_code, ea_code = {{ EA = Ra + Rb; }}, mem_flags = [], inst_flags = []) {{ (header_output, decoder_output, decode_block, exec_output) = \ GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, - 'MemOp', 'Store', mem_flags, inst_flags) + 'MemIndexOp', 'Store', mem_flags, inst_flags) }}; @@ -262,7 +262,7 @@ def format LoadIndexUpdateOp(memacc_code, ea_code = {{ EA = Ra + Rb; }}, # Generate the class (header_output, decoder_output, decode_block, exec_output) = \ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - base_class = 'MemOp', + base_class = 'MemIndexOp', exec_template_base = 'Load') }}; @@ -276,7 +276,7 @@ def format StoreIndexUpdateOp(memacc_code, ea_code = {{ EA = Ra + Rb; }}, # Generate the class (header_output, decoder_output, decode_block, exec_output) = \ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - base_class = 'MemOp', + base_class = 'MemIndexOp', exec_template_base = 'Store') }}; @@ -299,6 +299,16 @@ def format StoreDispOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, }}; +def format LoadDispShiftOp(memacc_code, + ea_code = {{ EA = Ra + (disp << 2); }}, + ea_code_ra0 = {{ EA = (disp << 2); }}, + mem_flags = [], inst_flags = []) {{ + (header_output, decoder_output, decode_block, exec_output) = \ + GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, + 'MemDispShiftOp', 'Load', mem_flags, inst_flags) +}}; + + def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, mem_flags = [], inst_flags = []) {{ -- 2.30.2