From 38b0b99a72d50cd71ce944236c5fe3e3c5eec4b2 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 9 Apr 2022 21:16:40 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index c3d5bf52d..b402f41a0 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -126,6 +126,26 @@ example. For SVP64 there is insufficient space to make the SVP64 Prefix "self-describing", and consequently every single Scalar instruction had to be individually analysed, by rote, to craft an EXTRA Field Mapping. This process was semi-automated and is described in this section. +The final results, which are part of the SVP64 Specification, are here: + +* [[openpower/opcode_regs_deduped]] + +Firstly, every instruction's mnemonic (`add RT, RA, RB`) was analysed +from reading the markdown formatted version of the Scalar pseudocode +which is machine-readable and found in [[openpower/isatables]]. The +analysis gives, by instruction, a "Register Profile". `add RT, RA, RB` +for example is given a designation `RM-2R-1W` because it requires +two GPR reads and one GPR write. + +Secondly, the total number of registers was added up (2R-1W is 3 registers) +and if less than or equal to three then that instruction could be given an +EXTRA3 designation. Four or more is given an EXTRA2 designation because +there are only 9 bits available. + +Thirdly, a packing format was decided: for 2R-1W an EXTRA3 indexing +could have been decided +that RA would be indexed 0 (EXTRA bits 0-2), RB indexed 1 (EXTRA bits 3-5) +and RT indexed 2 (EXTRA bits 6-8). # Single Predication -- 2.30.2