From 38d5245a4dc56d76bae7c045ec8b68bf253eb036 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 14 May 2021 20:29:35 +0100 Subject: [PATCH] add first FP load test, still a lot TODO --- src/openpower/decoder/isa/test_caller.py | 5 +- src/openpower/decoder/isa/test_caller_fp.py | 52 +++++++++++++++++++ .../decoder/isa/test_caller_svp64.py | 1 + src/openpower/decoder/power_enums.py | 15 ++++-- 4 files changed, 66 insertions(+), 7 deletions(-) create mode 100644 src/openpower/decoder/isa/test_caller_fp.py diff --git a/src/openpower/decoder/isa/test_caller.py b/src/openpower/decoder/isa/test_caller.py index 710fc6c0..efb6275f 100644 --- a/src/openpower/decoder/isa/test_caller.py +++ b/src/openpower/decoder/isa/test_caller.py @@ -17,7 +17,8 @@ class Register: self.num = num def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False, - initial_cr=0,mem=None): + initial_cr=0, mem=None, + initial_fprs=None): if initial_sprs is None: initial_sprs = {} m = Module() @@ -35,13 +36,13 @@ def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False, initial_insns=gen, respect_pc=True, initial_svstate=svstate, initial_mem=mem, + fpregfile=initial_fprs, disassembly=insncode, bigendian=0, mmu=mmu) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) - def process(): yield pdecode2.dec.bigendian.eq(0) # little / big? diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py new file mode 100644 index 00000000..7468cc51 --- /dev/null +++ b/src/openpower/decoder/isa/test_caller_fp.py @@ -0,0 +1,52 @@ +from nmigen import Module, Signal +from nmigen.back.pysim import Simulator, Delay, Settle +from nmutil.formaltest import FHDLTestCase +import unittest +from openpower.decoder.isa.caller import ISACaller +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.decoder.isa.caller import ISACaller, SVP64State +from openpower.decoder.selectable_int import SelectableInt +from openpower.decoder.orderedset import OrderedSet +from openpower.decoder.isa.all import ISA +from openpower.decoder.isa.test_caller import Register, run_tst +from copy import deepcopy + + +class DecoderTestCase(FHDLTestCase): + + def _check_regs(self, sim, expected_int, expected_fpr): + for i in range(32): + self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) + for i in range(32): + self.assertEqual(sim.fpr(i), SelectableInt(expected_fpr[i], 64)) + + def test_fpload(self): + """>>> lst = ["lfsx 1, 0, 0x0008", + ] + """ + lst = ["lfsx 1, 0, 0x0008", + ] + initial_mem = {0x0000: (0x4040266666666666, 8), + 0x0008: (0xabcdef0187654321, 8), + 0x0020: (0x1828384822324252, 8), + } + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_mem=initial_mem) + print(sim.fpr(1)) + self.assertEqual(sim.fpr(1), SelectableInt(0x4040266666666666, 64)) + + def run_tst_program(self, prog, initial_regs=None, + initial_mem=None): + if initial_regs is None: + initial_regs = [0] * 32 + simulator = run_tst(prog, initial_regs, mem=initial_mem) + simulator.gpr.dump() + simulator.fpr.dump() + return simulator + + +if __name__ == "__main__": + unittest.main() diff --git a/src/openpower/decoder/isa/test_caller_svp64.py b/src/openpower/decoder/isa/test_caller_svp64.py index 3e240de1..a8e94c33 100644 --- a/src/openpower/decoder/isa/test_caller_svp64.py +++ b/src/openpower/decoder/isa/test_caller_svp64.py @@ -15,6 +15,7 @@ from openpower.sv.trans.svp64 import SVP64Asm from openpower.consts import SVP64CROffs from copy import deepcopy + class DecoderTestCase(FHDLTestCase): def _check_regs(self, sim, expected): diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index da259953..f7e8ce1c 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -219,11 +219,16 @@ _insns = [ "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo", "divweu", "divweuo", "divwo", "divwu", "divwuo", "eqv", "extsb", "extsh", "extsw", "extswsli", "hrfid", "icbi", "icbt", "isel", "isync", - "lbarx", "lbz", "lbzu", "lbzux", "lbzx", "ld", "ldarx", "ldbrx", - "ldu", "ldux", "ldx", "lha", "lharx", "lhau", "lhaux", "lhax", - "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", "lwa", "lwarx", "lwaux", - "lwax", "lwbrx", "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", "mcrf", "mcrxr", - "mcrxrx", "mfcr/mfocrf", "mfmsr", "mfspr", "modsd", "modsw", "modud", + "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte + "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double + "lfs", "lfsx", "lfsu", "lfsux", # FP load single + "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double + "lha", "lharx", "lhau", "lhaux", "lhax", # load half + "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half + "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word + "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word + "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", + "mfmsr", "mfspr", "modsd", "modsw", "modud", "moduw", "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr", "mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo", "mulli", "mullw", "mullwo", "nand", "neg", "nego", "nop", "nor", "or", "orc", "ori", "oris", -- 2.30.2