From 38e92eb92b28bd0605a6bd52c8ccf353a5729ef6 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 26 Mar 2013 23:05:46 +0100 Subject: [PATCH] altera_quartus: fix clock domain name --- mibuild/altera_quartus.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index f1d366df..4fc78550 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -14,7 +14,7 @@ def _add_period_constraint(platform, clk, period): class CRG_SE(SimpleCRG): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) - _add_period_constraint(platform, self.cd.clk, period) + _add_period_constraint(platform, self.cd_sys.clk, period) def _format_constraint(c): if isinstance(c, Pins): -- 2.30.2