From 38f7ee5a22227452bfaeb83ea2eaea399ea8cc49 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 21 Apr 2023 22:40:47 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index e2765fb5f..73a494b66 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -187,10 +187,11 @@ such large numbers of registers, even for Multi-Issue microarchitectures. **Summary of Simple-V Opcode space** * 75% of one Major Opcode (equivalent to the rest of EXT017) -* Five 6-bit XO 32-bit operations. +* Five 6-bit XO 32-bit "Management" operations. No further opcode space *for Simple-V* is envisaged to be required for -at least the next decade (including if added on VSX) +at least the next decade (including if added on VSX). EXT1xx variants +of the Management Operations are anticipated for a future revision. **Simple-V SPRs** -- 2.30.2