From 390db632b52d1fb4ba880762cb13c4ba1dd38839 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 Jul 2020 20:56:55 +0100
Subject: [PATCH] update comments

---
 src/soc/litex/sim.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/litex/sim.py b/src/soc/litex/sim.py
index 9640c58a..1a4a2d66 100644
--- a/src/soc/litex/sim.py
+++ b/src/soc/litex/sim.py
@@ -63,7 +63,7 @@ class SoCSMP(SoCCore):
 
         # SoCCore --------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
-            cpu_type                 = "microwatt", # XXX use None for now libre_soc
+            cpu_type                 = "microwatt", # XXX use microwatt
             cpu_variant              = cpu_variant,
             cpu_cls                  = LibreSOC,
             uart_name                = "sim",
-- 
2.30.2