From 390e18b3b62b53f3cedc88c53e42b7771bb5bb2e Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 19 Apr 2023 20:21:10 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls012.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn index b7738b6cd..0ada13e41 100644 --- a/openpower/sv/rfc/ls012.mdwn +++ b/openpower/sv/rfc/ls012.mdwn @@ -184,6 +184,9 @@ cascading-option-multipliers (SIMD width, bitwidth, saturation, HI/LO) are abstracted out to RISC-paradigm Prefixing, leaving just absolute-diff-accumulate, min-max, average-add etc. as "basic primitives". +The min/max set are under their own RFC, [[ls013]]. They are sufficent +high priority: fmax requires an astounding 32 SFFS instructions. + ## Twin-Butterfly FFT/DCT/DFT for DSP/HPC/AI/AV The number of uses in Computer Science for DCT, NTT, FFT and DFT, @@ -309,7 +312,6 @@ Register Operand is needed). Realistically these high-value instructions should be proposed in EXT2xx where their XO cost does not overwhelm EXT0xx. - ## (f)mv.swizzle [[sv/mv.swizzle]] is dicey. It is a 2-in 2-out operation whose value -- 2.30.2