From 3927009c40f067c350d78feab58940319ece71d2 Mon Sep 17 00:00:00 2001
From: Tobias Platen <tplaten@posteo.de>
Date: Wed, 23 Mar 2022 17:15:07 +0100
Subject: [PATCH] allow using external core

---
 Makefile        | 23 ++++++++++++++++----
 core_dummy.vhdl | 58 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 77 insertions(+), 4 deletions(-)
 create mode 100644 core_dummy.vhdl

diff --git a/Makefile b/Makefile
index a6834c5..fcc4258 100644
--- a/Makefile
+++ b/Makefile
@@ -226,11 +226,26 @@ CLK_FREQUENCY=50000000
 clkgen=fpga/clk_gen_bypass.vhd
 endif
 
-fpga_files = fpga/soc_reset.vhdl \
-	fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
-	nonrandom.vhdl
 
-synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
+
+#--
+# use an alternative core (in verilog)
+EXTERNAL_CORE=true
+ifeq ($(EXTERNAL_CORE),false)
+
+    fpga_files = fpga/soc_reset.vhdl \
+		fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
+		nonrandom.vhdl
+
+	synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
+else
+    util_files = decode_types.vhdl common.vhdl wishbone_types.vhdl utils.vhdl \
+                core_dummy.vhdl
+    fpga_files = $(_fpga_files) $(_soc_files)
+    synth_files = $(util_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
+    soc_extra_v = external_core_top.v
+endif
+#--
 
 microwatt.json: $(synth_files) $(RAM_INIT_FILE) $(soc_extra_v)
 	$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)"
diff --git a/core_dummy.vhdl b/core_dummy.vhdl
new file mode 100644
index 0000000..8967bb7
--- /dev/null
+++ b/core_dummy.vhdl
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.common.all;
+use work.wishbone_types.all;
+
+entity core is
+    generic (
+        SIM : boolean := false;
+	DISABLE_FLATTEN : boolean := false;
+        EX1_BYPASS : boolean := true;
+        HAS_FPU : boolean := true;
+        HAS_BTC : boolean := true;
+	RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
+	ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
+        LOG_LENGTH : natural := 512
+        );
+    port (
+        clk          : in std_ulogic;
+        rst          : in std_ulogic;
+
+	-- Alternate reset (0xffff0000) for use by DRAM init fw
+	alt_reset    : in std_ulogic;
+
+	-- Wishbone interface
+        wishbone_insn_in  : in wishbone_slave_out;
+        wishbone_insn_out : out wishbone_master_out;
+
+        wishbone_data_in  : in wishbone_slave_out;
+        wishbone_data_out : out wishbone_master_out;
+
+	dmi_addr	: in std_ulogic_vector(3 downto 0);
+	dmi_din	        : in std_ulogic_vector(63 downto 0);
+	dmi_dout	: out std_ulogic_vector(63 downto 0);
+	dmi_req	        : in std_ulogic;
+	dmi_wr		: in std_ulogic;
+	dmi_ack	        : out std_ulogic;
+
+	ext_irq		: in std_ulogic;
+
+	terminated_out   : out std_logic;
+
+    -- for verilator debugging
+    nia_req: out std_ulogic;
+    nia: out std_ulogic_vector(63 downto 0);
+    msr_o: out std_ulogic_vector(63 downto 0);
+    insn: out std_ulogic_vector(31 downto 0);
+        ldst_req: out std_ulogic;
+        ldst_addr: out std_ulogic_vector(63 downto 0)
+        );
+end core;
+
+architecture behave of core is
+begin
+
+end behave;
-- 
2.30.2