From 39406c4c73c08eedd0d12a3204c2c43194f5a82a Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 8 May 2022 21:16:02 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 20cd6a836..d38504f3a 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -836,7 +836,9 @@ and CPU the answer is quite likely to be "yes", which is interesting in and of itself. Fortunately, the associated L1 Cache with TLB Translation does not have to be large, and the actual RADIX Tree Walk need not explicitly be done by the PEs, it can be handled by the main -CPU as a software-extension. +CPU as a software-extension: PEs generate a TLB Miss notification +to the main CPU over OpenCAPI, and the main CPU feeds back the new +TLB entries to the PE in response. **Use-case: Matrix and Convolutions** -- 2.30.2