From 3947809e309f4aa930f9be90bc40f951b348053a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 15 Oct 2020 18:11:11 +0100 Subject: [PATCH] wrong pspec variable in selecting pll clock --- src/soc/simple/issuer.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 0d1fa1f2..ae6c24bf 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -453,7 +453,7 @@ class TestIssuer(Elaboratable): self.clksel = ClockSelect() # PLL direct clock or not - self.pll_en = hasattr(pspec, "use_pll") and pspec.pll_en + self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll def elaborate(self, platform): m = Module() -- 2.30.2