From 396550dfe068f8ed21c584f3c364dd0b0ce38151 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 1 Jun 2020 20:14:06 +0100 Subject: [PATCH] remove zero/invert from ShiftRot Input Record --- src/soc/fu/common_input_stage.py | 12 ++++++++---- src/soc/fu/common_output_stage.py | 11 +++++++---- src/soc/fu/shift_rot/sr_input_record.py | 8 -------- 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py index b0ea4b32..cd162096 100644 --- a/src/soc/fu/common_input_stage.py +++ b/src/soc/fu/common_input_stage.py @@ -12,15 +12,19 @@ class CommonInputStage(PipeModBase): def elaborate(self, platform): m = Module() comb = m.d.comb + op = self.i.ctx.op ##### operand A ##### # operand a to be as-is or inverted a = Signal.like(self.i.a) - with m.If(self.i.ctx.op.invert_a): - comb += a.eq(~self.i.a) - with m.Else(): + if hasattr(op, "invert_a"): + with m.If(op.invert_a): + comb += a.eq(~self.i.a) + with m.Else(): + comb += a.eq(self.i.a) + else: comb += a.eq(self.i.a) comb += self.o.a.eq(a) @@ -29,7 +33,7 @@ class CommonInputStage(PipeModBase): # either copy incoming carry or set to 1/0 as defined by op if hasattr(self.i, "xer_ca"): # hack (for now - for LogicalInputData) - with m.Switch(self.i.ctx.op.input_carry): + with m.Switch(op.input_carry): with m.Case(CryIn.ZERO): comb += self.o.xer_ca.eq(0b00) with m.Case(CryIn.ONE): diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index 576f88a5..1a28956f 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -17,10 +17,13 @@ class CommonOutputStage(PipeModBase): # op requests inversion of the output o = Signal.like(self.i.o) - with m.If(op.invert_out): - comb += o.eq(~self.i.o.data) - with m.Else(): - comb += o.eq(self.i.o.data) + if hasattr(op, "invert_out"): + with m.If(op.invert_out): + comb += o.eq(~self.i.o.data) + with m.Else(): + comb += o.eq(self.i.o.data) + else: + comb += o.eq(self.i.o.data) # target register if 32-bit is only the 32 LSBs target = Signal(64, reset_less=True) diff --git a/src/soc/fu/shift_rot/sr_input_record.py b/src/soc/fu/shift_rot/sr_input_record.py index a692c418..8263410c 100644 --- a/src/soc/fu/shift_rot/sr_input_record.py +++ b/src/soc/fu/shift_rot/sr_input_record.py @@ -19,10 +19,7 @@ class CompSROpSubset(Record): ('lk', 1), ('rc', Layout((("rc", 1), ("rc_ok", 1)))), ('oe', Layout((("oe", 1), ("oe_ok", 1)))), - ('invert_a', 1), - ('zero_a', 1), ('write_cr', Layout((("data", 3), ("ok", 1)))), # Data - ('invert_out', 1), ('input_carry', CryIn), ('output_carry', 1), ('input_cr', 1), @@ -42,9 +39,6 @@ class CompSROpSubset(Record): #self.cr = Signal(32, reset_less = True #self.xerc = XerBits( self.lk.reset_less = True - self.zero_a.reset_less = True - self.invert_a.reset_less = True - self.invert_out.reset_less = True self.input_carry.reset_less = True self.output_carry.reset_less = True self.input_cr.reset_less = True @@ -69,8 +63,6 @@ class CompSROpSubset(Record): #self.cr, #self.xerc, self.lk, - self.invert_a, - self.invert_out, self.input_carry, self.output_carry, self.input_cr, -- 2.30.2