From 396b71a9034c475f4f3e1d97991d585b38d0408d Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Fri, 22 May 2020 01:11:00 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise
 that RA (src1) can be zero

---
 90/3cb2a3176514b5e7d15043f571b6e649f24587 | 91 +++++++++++++++++++++++
 1 file changed, 91 insertions(+)
 create mode 100644 90/3cb2a3176514b5e7d15043f571b6e649f24587

diff --git a/90/3cb2a3176514b5e7d15043f571b6e649f24587 b/90/3cb2a3176514b5e7d15043f571b6e649f24587
new file mode 100644
index 0000000..4639121
--- /dev/null
+++ b/90/3cb2a3176514b5e7d15043f571b6e649f24587
@@ -0,0 +1,91 @@
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+From: bugzilla-daemon@libre-soc.org
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Fri, 22 May 2020 01:11:00 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: cestrauss@gmail.com
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: cestrauss@gmail.com
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+Message-ID: <bug-336-13-h8xJkKskcQ@https.bugs.libre-soc.org/>
+In-Reply-To: <bug-336-13@https.bugs.libre-soc.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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-- 
2.30.2