From 3991e9cd06e71fadc59c8bc1039daf9d38fbad06 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 26 Jun 2022 09:35:17 +0100 Subject: [PATCH] svremap only takes 7 args not 8, same as in svp64_fft.py fix in svp64_dct.py --- src/openpower/decoder/isa/test_caller_svp64_dct.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_dct.py b/src/openpower/decoder/isa/test_caller_svp64_dct.py index 564ed5af..11260e59 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_dct.py +++ b/src/openpower/decoder/isa/test_caller_svp64_dct.py @@ -924,7 +924,7 @@ class DCTTestCase(FHDLTestCase): def test_sv_remap_fpmadds_ldbrev_dct_8_mode_4(self): """>>> lst = [# LOAD bit-reversed with half-swap "svshape 8, 1, 1, 6, 0", - "svremap 1, 0, 0, 0, 0, 0, 0, 0", + "svremap 1, 0, 0, 0, 0, 0, 0", "sv.lfssh 0.v, 4(1), 2", # Inner butterfly, twin +/- MUL-ADD-SUB "svremap 31, 1, 0, 2, 0, 1, 1", @@ -942,7 +942,7 @@ class DCTTestCase(FHDLTestCase): """ lst = SVP64Asm( ["addi 1, 0, 0x000", "svshape 8, 1, 1, 6, 0", - "svremap 1, 0, 0, 0, 0, 0, 0, 1", + "svremap 1, 0, 0, 0, 0, 0, 0", "sv.lfssh 0.v, 4(1), 2", "svremap 31, 1, 0, 2, 0, 1, 1", "svshape 8, 1, 1, 4, 0", @@ -1014,7 +1014,7 @@ class DCTTestCase(FHDLTestCase): def test_sv_remap_fpmadds_ldbrev_idct_8_mode_4(self): """>>> lst = [# LOAD bit-reversed with half-swap "svshape 8, 1, 1, 14, 0", - "svremap 1, 0, 0, 0, 0, 0, 0, 0", + "svremap 1, 0, 0, 0, 0, 0, 0", "sv.lfssh 0.v, 4(1), 2", # Outer butterfly, iterative sum "svremap 31, 0, 1, 2, 1, 0, 1", @@ -1032,7 +1032,7 @@ class DCTTestCase(FHDLTestCase): """ lst = SVP64Asm( ["addi 1, 0, 0x000", "svshape 8, 1, 1, 14, 0", - "svremap 1, 0, 0, 0, 0, 0, 0, 1", + "svremap 1, 0, 0, 0, 0, 0, 0", "sv.lfssh 0.v, 4(1), 2", "svremap 31, 0, 1, 2, 1, 0, 1", "svshape 8, 1, 1, 11, 0", -- 2.30.2