From 39a32f562d9a735e7fd4db30bd95a342e4d8b377 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Mon, 3 Feb 2020 12:13:20 -0500 Subject: [PATCH] Rename partition_combiner to eq_combiner --- .../part_cmp/{partition_combiner.py => eq_combiner.py} | 2 +- .../part_cmp/formal/{proof_combiner.py => proof_eq.py} | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) rename src/ieee754/part_cmp/{partition_combiner.py => eq_combiner.py} (98%) rename src/ieee754/part_cmp/formal/{proof_combiner.py => proof_eq.py} (92%) diff --git a/src/ieee754/part_cmp/partition_combiner.py b/src/ieee754/part_cmp/eq_combiner.py similarity index 98% rename from src/ieee754/part_cmp/partition_combiner.py rename to src/ieee754/part_cmp/eq_combiner.py index 2608097b..07b73429 100644 --- a/src/ieee754/part_cmp/partition_combiner.py +++ b/src/ieee754/part_cmp/eq_combiner.py @@ -24,7 +24,7 @@ class Twomux(Elaboratable): #equals.py's giant switch statement. The idea is to use a tree of two #input/two output multiplexors and or gates to select whether each #signal is or isn't combined with its neighbors. -class Combiner(Elaboratable): +class EQCombiner(Elaboratable): def __init__(self, width): self.width = width self.neqs = Signal(width, reset_less=True) diff --git a/src/ieee754/part_cmp/formal/proof_combiner.py b/src/ieee754/part_cmp/formal/proof_eq.py similarity index 92% rename from src/ieee754/part_cmp/formal/proof_combiner.py rename to src/ieee754/part_cmp/formal/proof_eq.py index 37022ef4..b72bad6d 100644 --- a/src/ieee754/part_cmp/formal/proof_combiner.py +++ b/src/ieee754/part_cmp/formal/proof_eq.py @@ -6,7 +6,7 @@ from nmigen.asserts import Assert, AnyConst from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil -from ieee754.part_cmp.partition_combiner import Combiner +from ieee754.part_cmp.eq_combiner import EQCombiner import unittest @@ -31,7 +31,7 @@ class CombinerDriver(Elaboratable): gates.eq(AnyConst(width)), neqs.eq(~eqs)] - m.submodules.dut = dut = Combiner(width) + m.submodules.dut = dut = EQCombiner(width) with m.Switch(gates): with m.Case(0b11): @@ -61,12 +61,12 @@ class CombinerDriver(Elaboratable): return m -class CombinerTestCase(FHDLTestCase): +class EQCombinerTestCase(FHDLTestCase): def test_combiner(self): module = CombinerDriver() self.assertFormal(module, mode="bmc", depth=4) def test_ilang(self): - dut = Combiner(3) + dut = EQCombiner(3) vl = rtlil.convert(dut, ports=dut.ports()) with open("partition_combiner.il", "w") as f: f.write(vl) -- 2.30.2