From 39a5b6998538f5a436b2b9f7e30e4f8937aaaea9 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Wed, 28 May 2014 16:02:12 -0700 Subject: [PATCH] i965: Split gen6 depth hiz state out from brw We will program the gen6 hiz depth state differently to enable layered rendering on gen6. v2: * Remove unneeded gen6_emit_depthbuffer as suggested by Topi Signed-off-by: Jordan Justen Reviewed-by: Topi Pohjolainen Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/Makefile.sources | 1 + src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i965/brw_context.h | 10 ++ src/mesa/drivers/dri/i965/gen6_depth_state.c | 176 +++++++++++++++++++ 4 files changed, 188 insertions(+), 1 deletion(-) create mode 100644 src/mesa/drivers/dri/i965/gen6_depth_state.c diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources index 40210b4474d..b91b81397bf 100644 --- a/src/mesa/drivers/dri/i965/Makefile.sources +++ b/src/mesa/drivers/dri/i965/Makefile.sources @@ -119,6 +119,7 @@ i965_FILES = \ gen6_blorp.cpp \ gen6_cc.c \ gen6_clip_state.c \ + gen6_depth_state.c \ gen6_depthstencil.c \ gen6_gs_state.c \ gen6_multisample_state.c \ diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 8d5740e3e8d..12f898abdb5 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -674,7 +674,7 @@ brwCreateContext(gl_api api, brw->vtbl.emit_depth_stencil_hiz = gen7_emit_depth_stencil_hiz; } else if (brw->gen >= 6) { gen6_init_vtable_surface_functions(brw); - brw->vtbl.emit_depth_stencil_hiz = brw_emit_depth_stencil_hiz; + brw->vtbl.emit_depth_stencil_hiz = gen6_emit_depth_stencil_hiz; } else { gen4_init_vtable_surface_functions(brw); brw->vtbl.emit_depth_stencil_hiz = brw_emit_depth_stencil_hiz; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 77977801735..602275c26ab 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1761,6 +1761,16 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw, uint32_t width, uint32_t height, uint32_t tile_x, uint32_t tile_y); +void +gen6_emit_depth_stencil_hiz(struct brw_context *brw, + struct intel_mipmap_tree *depth_mt, + uint32_t depth_offset, uint32_t depthbuffer_format, + uint32_t depth_surface_type, + struct intel_mipmap_tree *stencil_mt, + bool hiz, bool separate_stencil, + uint32_t width, uint32_t height, + uint32_t tile_x, uint32_t tile_y); + void gen7_emit_depth_stencil_hiz(struct brw_context *brw, struct intel_mipmap_tree *depth_mt, diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c new file mode 100644 index 00000000000..d37aae81044 --- /dev/null +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + + +#include "intel_batchbuffer.h" +#include "intel_fbo.h" +#include "intel_mipmap_tree.h" + +#include "brw_context.h" +#include "brw_state.h" +#include "brw_defines.h" + +#include "main/fbobject.h" +#include "main/glformats.h" + +void +gen6_emit_depth_stencil_hiz(struct brw_context *brw, + struct intel_mipmap_tree *depth_mt, + uint32_t depth_offset, uint32_t depthbuffer_format, + uint32_t depth_surface_type, + struct intel_mipmap_tree *stencil_mt, + bool hiz, bool separate_stencil, + uint32_t width, uint32_t height, + uint32_t tile_x, uint32_t tile_y) +{ + /* Enable the hiz bit if we're doing separate stencil, because it and the + * separate stencil bit must have the same value. From Section 2.11.5.6.1.1 + * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable": + * [DevIL]: If this field is enabled, Hierarchical Depth Buffer + * Enable must also be enabled. + * + * [DevGT]: This field must be set to the same value (enabled or + * disabled) as Hierarchical Depth Buffer Enable + */ + bool enable_hiz_ss = hiz || separate_stencil; + + + /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both + * non-pipelined state that will need the PIPE_CONTROL workaround. + */ + if (brw->gen == 6) { + intel_emit_post_sync_nonzero_flush(brw); + intel_emit_depth_stall_flushes(brw); + } + + unsigned int len; + if (brw->gen >= 6) + len = 7; + else if (brw->is_g4x || brw->gen == 5) + len = 6; + else + len = 5; + + BEGIN_BATCH(len); + OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); + OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) | + (depthbuffer_format << 18) | + ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */ + ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */ + (BRW_TILEWALK_YMAJOR << 26) | + ((depth_mt ? depth_mt->tiling != I915_TILING_NONE : 1) + << 27) | + (depth_surface_type << 29)); + + if (depth_mt) { + OUT_RELOC(depth_mt->bo, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + depth_offset); + } else { + OUT_BATCH(0); + } + + OUT_BATCH(((width + tile_x - 1) << 6) | + ((height + tile_y - 1) << 19)); + OUT_BATCH(0); + + if (brw->is_g4x || brw->gen >= 5) + OUT_BATCH(tile_x | (tile_y << 16)); + else + assert(tile_x == 0 && tile_y == 0); + + if (brw->gen >= 6) + OUT_BATCH(0); + + ADVANCE_BATCH(); + + if (hiz || separate_stencil) { + /* + * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate + * stencil enable' and 'hiz enable' bits were set. Therefore we must + * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if + * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted; + * failure to do so causes hangs on gen5 and a stall on gen6. + */ + + /* Emit hiz buffer. */ + if (hiz) { + struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt; + BEGIN_BATCH(3); + OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); + OUT_BATCH(hiz_mt->pitch - 1); + OUT_RELOC(hiz_mt->bo, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + brw->depthstencil.hiz_offset); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(3); + OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } + + /* Emit stencil buffer. */ + if (separate_stencil) { + BEGIN_BATCH(3); + OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); + /* The stencil buffer has quirky pitch requirements. From Vol 2a, + * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch": + * The pitch must be set to 2x the value computed based on width, as + * the stencil buffer is stored with two rows interleaved. + */ + OUT_BATCH(2 * stencil_mt->pitch - 1); + OUT_RELOC(stencil_mt->bo, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + brw->depthstencil.stencil_offset); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(3); + OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } + } + + /* + * On Gen >= 6, emit clear params for safety. If using hiz, then clear + * params must be emitted. + * + * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS: + * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet + * when HiZ is enabled and the DEPTH_BUFFER_STATE changes. + */ + if (brw->gen >= 6 || hiz) { + if (brw->gen == 6) + intel_emit_post_sync_nonzero_flush(brw); + + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | + GEN5_DEPTH_CLEAR_VALID | + (2 - 2)); + OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0); + ADVANCE_BATCH(); + } +} -- 2.30.2