From 39ce39a298f576da8f4ccc97873a3a78f03cc4fe Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Jan 2020 13:00:17 +0100 Subject: [PATCH] soc_sdram: add l2_data_width parameter to set minimal l2_data_width to improve DRAM accesses efficiency. --- litex/soc/integration/soc_sdram.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index a4196ba3..2535e85d 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -26,12 +26,13 @@ class SoCSDRAM(SoCCore): } csr_map.update(SoCCore.csr_map) - def __init__(self, platform, clk_freq, l2_size=8192, **kwargs): + def __init__(self, platform, clk_freq, l2_size=8192, l2_data_width=128, **kwargs): SoCCore.__init__(self, platform, clk_freq, **kwargs) if not self.integrated_main_ram_size: if self.cpu_type is not None and self.csr_data_width > 32: raise NotImplementedError("BIOS supports SDRAM initialization only for csr_data_width<=32") - self.l2_size = l2_size + self.l2_size = l2_size + self.l2_data_width = l2_data_width self._sdram_phy = [] self._wb_sdram_ifs = [] @@ -99,7 +100,8 @@ class SoCSDRAM(SoCCore): self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size) # L2 Cache ----------------------------------------------------------------------------- - l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width)) + l2_data_width = max(port.data_width, self.l2_data_width) + l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(l2_data_width)) # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache. # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx... from litex.build.xilinx.vivado import XilinxVivadoToolchain -- 2.30.2