From 39d19ac2ae4ed189076e985c1385200259219f56 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 19 Sep 2022 21:56:44 +0100 Subject: [PATCH] print out reg num in _check_regs, useful debug --- src/openpower/decoder/isa/test_caller_svp64_predication.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_predication.py b/src/openpower/decoder/isa/test_caller_svp64_predication.py index 23db0a96..ba6906b4 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_predication.py +++ b/src/openpower/decoder/isa/test_caller_svp64_predication.py @@ -19,7 +19,9 @@ class DecoderTestCase(FHDLTestCase): def _check_regs(self, sim, expected): for i in range(32): - self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) + self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64), + "reg %d expected %x got %x" % \ + (i, sim.gpr(i).value, expected[i])) def tst_sv_load_store(self): lst = SVP64Asm(["addi 1, 0, 0x0010", -- 2.30.2