From 39d86cda8e3c43d3494f4c3ef0b7e77773617051 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 22 Apr 2019 16:37:40 +0100 Subject: [PATCH] use random selection for LFSR on write --- TLB/src/SetAssociativeCache.py | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/TLB/src/SetAssociativeCache.py b/TLB/src/SetAssociativeCache.py index f3b71efd..02a491b0 100644 --- a/TLB/src/SetAssociativeCache.py +++ b/TLB/src/SetAssociativeCache.py @@ -1,7 +1,7 @@ import sys sys.path.append("../src/ariane") -from nmigen import Array, Cat, Memory, Module, Signal +from nmigen import Array, Cat, Memory, Module, Signal, Mux from nmigen.compat.genlib import fsm from nmigen.cli import main from nmigen.cli import verilog, rtlil @@ -202,10 +202,20 @@ class SetAssociativeCache(): # and connect plru to encoder for write self.encoder.i.eq(self.plru.replace_en_o) ] + write_port = self.mem_array[self.encoder.o].w + else: + # use the LFSR to generate a random(ish) one of the mem array + lfsr_output = Signal(max=self.way_count) + lfsr_random = Signal(max=self.way_count) + m.d.comb += lfsr_output.eq(self.lfsr.state) # lose some bits + # address too big, limit to range of array + m.d.comb += lfsr_random.eq(Mux(lfsr_output > self.way_count, + lfsr_output - self.way_count, + lfsr_output)) + write_port = self.mem_array[lfsr_random].w # then if there is a match from the encoder, enable the selected write with m.If(self.encoder.single_match): - write_port = self.mem_array[self.encoder.o].w m.d.comb += write_port.en.eq(1) def write(self, m): @@ -243,6 +253,9 @@ class SetAssociativeCache(): m.d.comb += [ # Set what entry was hit self.plru.lu_hit.eq(self.encoder.o), ] + else: + m.d.comb += [ self.lfsr.enable.eq(self.enable), # enable LFSR + ] # ---- # connect hit/multiple hit to encoder output @@ -285,12 +298,12 @@ class SetAssociativeCache(): if __name__ == '__main__': - sac = SetAssociativeCache(4, 8, 4, 4) + sac = SetAssociativeCache(4, 8, 4, 6) vl = rtlil.convert(sac, ports=sac.ports()) with open("SetAssociativeCache.il", "w") as f: f.write(vl) - sac_lfsr = SetAssociativeCache(4, 8, 4, 4, True) + sac_lfsr = SetAssociativeCache(4, 8, 4, 6, True) vl = rtlil.convert(sac_lfsr, ports=sac_lfsr.ports()) with open("SetAssociativeCacheLFSR.il", "w") as f: f.write(vl) -- 2.30.2