From 39df725f731f75f488c75a4910169beb352213fb Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Sun, 6 Sep 2015 04:51:29 -0400 Subject: [PATCH] nvc0: always emit a full shader colormask Indications are that if the colormask indicates a single bit set on fermi, that value will always be read from $r0 instead of a potentially higher register (if e.g. green is set). Not to upset the counting logic, always set the header up with a full color mask for each RT. Such a situation can basically only ever happen with generated blit shaders. Fixes the following piglit on Fermi (Kepler is unaffected): fbo-stencil blit GL_DEPTH32F_STENCIL8 Signed-off-by: Ilia Mirkin Cc: "10.6 11.0" --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c index 12f1bb728d7..a168dd684ab 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c @@ -449,7 +449,7 @@ nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info) for (i = 0; i < info->numOutputs; ++i) { if (info->out[i].sn == TGSI_SEMANTIC_COLOR) - fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0]; + fp->hdr[18] |= 0xf << info->out[i].slot[0]; } fp->fp.early_z = info->prop.fp.earlyFragTests; -- 2.30.2