From 39f02e5b5f4f8c982ebf6f2333a0a5a4e5816576 Mon Sep 17 00:00:00 2001 From: Cole Poirier Date: Thu, 13 Aug 2020 11:45:25 -0700 Subject: [PATCH] move memory related types from mmu.py into new file mem_types.py as they are used by icache and dcache as well --- src/soc/experiment/mem_types.py | 103 +++++++++++++++++++++++++++++ src/soc/experiment/mmu.py | 112 +++----------------------------- 2 files changed, 111 insertions(+), 104 deletions(-) create mode 100644 src/soc/experiment/mem_types.py diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py new file mode 100644 index 00000000..bed4fffe --- /dev/null +++ b/src/soc/experiment/mem_types.py @@ -0,0 +1,103 @@ +"""mem_types + +based on Anton Blanchard microwatt common.vhdl + +""" +from nmigen.iocontrol import RecordObject + + +# type Loadstore1ToMmuType is record +# valid : std_ulogic; +# tlbie : std_ulogic; +# slbia : std_ulogic; +# mtspr : std_ulogic; +# iside : std_ulogic; +# load : std_ulogic; +# priv : std_ulogic; +# sprn : std_ulogic_vector(9 downto 0); +# addr : std_ulogic_vector(63 downto 0); +# rs : std_ulogic_vector(63 downto 0); +# end record; +class LoadStore1ToMmuType(RecordObject): + def __init__(self): + super().__init__() + self.valid = Signal() + self.tlbie = Signal() + self.slbia = Signal() + self.mtspr = Signal() + self.iside = Signal() + self.load = Signal() + self.priv = Signal() + self.sprn = Signal(10) + self.addr = Signal(64) + self.rs = Signal(64) + +# type MmuToLoadstore1Type is record +# done : std_ulogic; +# err : std_ulogic; +# invalid : std_ulogic; +# badtree : std_ulogic; +# segerr : std_ulogic; +# perm_error : std_ulogic; +# rc_error : std_ulogic; +# sprval : std_ulogic_vector(63 downto 0); +# end record; +class MmuToLoadStore1Type(RecordObject): + def __init__(self): + super().__init__() + self.done = Signal() + self.err = Signal() + self.invalid = Signal() + self.badtree = Signal() + self.segerr = Signal() + self.perm_error = Signal() + self.rc_error = Signal() + self.sprval = Signal(64) + +# type MmuToDcacheType is record +# valid : std_ulogic; +# tlbie : std_ulogic; +# doall : std_ulogic; +# tlbld : std_ulogic; +# addr : std_ulogic_vector(63 downto 0); +# pte : std_ulogic_vector(63 downto 0); +# end record; +class MmuToDcacheType(RecordObject): + def __init__(self): + super().__init__() + self.valid = Signal() + self.tlbie = Signal() + self.doall = Signal() + self.tlbld = Signal() + self.addr = Signal(64) + self.pte = Signal(64) + +# type DcacheToMmuType is record +# stall : std_ulogic; +# done : std_ulogic; +# err : std_ulogic; +# data : std_ulogic_vector(63 downto 0); +# end record; +class DcacheToMmuType(RecordObject): + def __init__(self): + super().__init__() + self.stall = Signal() + self.done = Signal() + self.err = Signal() + self.data = Signal(64) + + +# type MmuToIcacheType is record +# tlbld : std_ulogic; +# tlbie : std_ulogic; +# doall : std_ulogic; +# addr : std_ulogic_vector(63 downto 0); +# pte : std_ulogic_vector(63 downto 0); +# end record; +class MmuToIcacheType(RecordObject): + def __init__(self): + self.tlbld = Signal() + self.tlbie = Signal() + self.doall = Signal() + self.addr = Signal(64) + self.pte = Signal(64) diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index 9b36c17a..8b811068 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -4,120 +4,24 @@ based on Anton Blanchard microwatt mmu.vhdl """ from enum import Enum, unique -from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed, +from nmigen import (Module, Signal, Elaboratable, + Mux, Cat, Repl, signed, ResetSignal) from nmigen.cli import main from nmigen.iocontrol import RecordObject +from experiment.mem_types import LoadStore1ToMmuType, + MmuToLoadStore1Type, + MmuToDcacheType, + DcacheToMmuType, + MmuToIcacheType + # library ieee; use ieee.std_logic_1164.all; # use ieee.numeric_std.all; # library work; use work.common.all; -# start from common.vhdl -# type Loadstore1ToMmuType is record -# valid : std_ulogic; -# tlbie : std_ulogic; -# slbia : std_ulogic; -# mtspr : std_ulogic; -# iside : std_ulogic; -# load : std_ulogic; -# priv : std_ulogic; -# sprn : std_ulogic_vector(9 downto 0); -# addr : std_ulogic_vector(63 downto 0); -# rs : std_ulogic_vector(63 downto 0); -# end record; -class LoadStore1ToMmuType(RecordObject): - def __init__(self): - super().__init__() - self.valid = Signal() - self.tlbie = Signal() - self.slbia = Signal() - self.mtspr = Signal() - self.iside = Signal() - self.load = Signal() - self.priv = Signal() - self.sprn = Signal(10) - self.addr = Signal(64) - self.rs = Signal(64) - -# type MmuToLoadstore1Type is record -# done : std_ulogic; -# err : std_ulogic; -# invalid : std_ulogic; -# badtree : std_ulogic; -# segerr : std_ulogic; -# perm_error : std_ulogic; -# rc_error : std_ulogic; -# sprval : std_ulogic_vector(63 downto 0); -# end record; -class MmuToLoadStore1Type(RecordObject): - def __init__(self): - super().__init__() - self.done = Signal() - self.err = Signal() - self.invalid = Signal() - self.badtree = Signal() - self.segerr = Signal() - self.perm_error = Signal() - self.rc_error = Signal() - self.sprval = Signal(64) - -# type MmuToDcacheType is record -# valid : std_ulogic; -# tlbie : std_ulogic; -# doall : std_ulogic; -# tlbld : std_ulogic; -# addr : std_ulogic_vector(63 downto 0); -# pte : std_ulogic_vector(63 downto 0); -# end record; -class MmuToDcacheType(RecordObject): - def __init__(self): - super().__init__() - self.valid = Signal() - self.tlbie = Signal() - self.doall = Signal() - self.tlbld = Signal() - self.addr = Signal(64) - self.pte = Signal(64) - -# type DcacheToMmuType is record -# stall : std_ulogic; -# done : std_ulogic; -# err : std_ulogic; -# data : std_ulogic_vector(63 downto 0); -# end record; -class DcacheToMmuType(RecordObject): - def __init__(self): - super().__init__() - self.stall = Signal() - self.done = Signal() - self.err = Signal() - self.data = Signal(64) - - -# type MmuToIcacheType is record -# tlbld : std_ulogic; -# tlbie : std_ulogic; -# doall : std_ulogic; -# addr : std_ulogic_vector(63 downto 0); -# pte : std_ulogic_vector(63 downto 0); -# end record; -class MmuToIcacheType(RecordObject): - def __init__(self): - self.tlbld = Signal() - self.tlbie = Signal() - self.doall = Signal() - self.addr = Signal(64) - self.pte = Signal(64) -# end from common.vhdl - - - - - - # -- Radix MMU # -- Supports 4-level trees as in arch 3.0B, but not the # -- two-step translation -- 2.30.2