From 39f8d6aa73fd74610eeb354f76532fa2413ba2a4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 4 Sep 2020 16:16:40 +0100 Subject: [PATCH] bring out XICS ICS interrupt levels so that they can be wired to peripherals --- src/soc/simple/issuer.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index ea76bbe1..a60bf38a 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -49,6 +49,7 @@ class TestIssuer(Elaboratable): if self.xics: self.xics_icp = XICS_ICP() self.xics_ics = XICS_ICS() + self.int_level_i = self.xics_ics.int_level_i # main instruction core self.core = core = NonProductionCore(pspec) @@ -325,6 +326,7 @@ class TestIssuer(Elaboratable): if self.xics: ports += list(self.xics_icp.bus.fields.values()) ports += list(self.xics_ics.bus.fields.values()) + ports.append(self.int_level_i) return ports -- 2.30.2