From 39f9b5d8214af5e9c06923b10baab112257a2126 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 7 Jul 2021 16:43:40 +0100 Subject: [PATCH] clean up imports and unit test name --- src/openpower/decoder/isa/test_caller_svp64_fft.py | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py index 181de643..df93c763 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fft.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py @@ -2,17 +2,12 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State +from openpower.decoder.isa.caller import SVP64State from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.decoder.isa.test_caller import run_tst from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs from copy import deepcopy from openpower.decoder.helpers import fp64toselectable from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE @@ -66,7 +61,7 @@ def transform_radix2(vec, exptable): return vec -class DecoderTestCase(FHDLTestCase): +class FFTTestCase(FHDLTestCase): def _check_regs(self, sim, expected): for i in range(32): -- 2.30.2