From 39fb7faf959a808f73bf3b27f4bafd1613e76f13 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Michel=20D=C3=A4nzer?= Date: Wed, 12 Sep 2012 17:33:30 +0200 Subject: [PATCH] radeon/llvm: Match int_AMDGPU_floor for SI. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Michel Dänzer Reviewed-by: Tom Stellard --- src/gallium/drivers/radeon/SIInstructions.td | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index d663c634f4f..4b76dad0eec 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -530,7 +530,9 @@ defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", []>; defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", [(set VReg_32:$dst, (frint AllReg_32:$src0))] >; -defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", []>; +defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", + [(set VReg_32:$dst, (int_AMDGPU_floor AllReg_32:$src0))] +>; defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", [(set VReg_32:$dst, (fexp2 AllReg_32:$src0))] >; -- 2.30.2