From 3a1920153c22198b0747ffc43e3449ae2a96bc9e Mon Sep 17 00:00:00 2001 From: R Veera Kumar Date: Fri, 26 Nov 2021 07:23:29 +0530 Subject: [PATCH] Make carry_out32 variable boolean and expected state ca var less confusing --- src/openpower/test/alu/alu_cases.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py index ca68fd2e..45d2f822 100644 --- a/src/openpower/test/alu/alu_cases.py +++ b/src/openpower/test/alu/alu_cases.py @@ -295,8 +295,8 @@ class ALUTestCase(TestAccumulatorBase): # (if it overflows, we don't care, because this is not addeo) result = 1 + initial_regs[6] + initial_regs[7] carry_out = result & (1<<64) != 0 # detect 65th bit as carry-out? - carry_out32 = ((initial_regs[6] & 0xffff_ffff) + \ - (initial_regs[7] & 0xffff_ffff)) & (1<<32) + carry_out32 = (initial_regs[6] & 0xffff_ffff) + \ + (initial_regs[7] & 0xffff_ffff) & (1<<32) != 0 result = result & ((1<<64)-1) # round eq = 0 gt = 0 @@ -313,7 +313,7 @@ class ALUTestCase(TestAccumulatorBase): e.intregs[7] = initial_regs[7] # should be same as initial e.intregs[5] = result # carry_out goes into bit 0 of ca, carry_out32 into bit 1 - e.ca = carry_out | (carry_out32>>31) + e.ca = carry_out | (carry_out32<<1) # eq goes into bit 1 of CR0, gt into bit 2, le into bit 3. # SO goes into bit 0 but overflow doesn't occur here [we hope] e.crregs[0] = (eq<<1) | (gt<<2) | (le<<3) -- 2.30.2