From 3a1921d77d0a3aefe65e7b0499dfb71cc9867942 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Thu, 4 Feb 2021 20:19:39 +0100 Subject: [PATCH] pass SPR MicroOp to MMU function unit --- src/soc/decoder/power_decoder2.py | 11 ++++++++++- src/soc/simple/core.py | 3 +++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 2f6c0bde..bfe9eda4 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -889,7 +889,16 @@ class PowerDecodeSubset(Elaboratable): # set up instruction type # no op: defaults to OP_ILLEGAL - comb += self.do_copy("insn_type", self.op_get("internal_op")) + if self.fn_name=="MMU": + # mmu is special case: needs SPR opcode as well + mmu0 = self.mmu0_spr_dec + with m.If(((mmu0.dec.op.internal_op == MicrOp.OP_MTSPR) | + (mmu0.dec.op.internal_op == MicrOp.OP_MFSPR))): + comb += self.do_copy("insn_type", mmu0.op_get("internal_op")) + with m.Else(): + comb += self.do_copy("insn_type", self.op_get("internal_op")) + else: + comb += self.do_copy("insn_type", self.op_get("internal_op")) # function unit for decoded instruction: requires minor redirect # for SPR set/get diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 9d115a3d..d3a66bb1 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -114,6 +114,9 @@ class NonProductionCore(Elaboratable): state=self.state) self.des[funame] = self.decoders[funame].do + if "mmu0" in self.decoders: + self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"] + def elaborate(self, platform): m = Module() # for testing purposes, to cut down on build time in coriolis2 -- 2.30.2