From 3a2430e05b1503653ae09cb21feb2a0d4ea51ec7 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Wed, 15 Nov 2017 08:51:03 +0100 Subject: [PATCH] x86: drop VEXI4_Fixup() The low four bits of an immediate being set when the high bits specify a fourth register operand is not a problem: CPUs ignore these bits rather than raising #UD. Take care of incrementing codep in OP_EX_VexW() instead. --- gas/ChangeLog | 5 ++ gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/noextreg.d | 12 +++++ gas/testsuite/gas/i386/noextreg.s | 10 ++++ opcodes/ChangeLog | 8 +++ opcodes/i386-dis.c | 87 +++++++++++++------------------ 6 files changed, 73 insertions(+), 50 deletions(-) create mode 100644 gas/testsuite/gas/i386/noextreg.d create mode 100644 gas/testsuite/gas/i386/noextreg.s diff --git a/gas/ChangeLog b/gas/ChangeLog index 66bc0349052..3624da7de97 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2017-11-15 Jan Beulich + + * testsuite/gas/i386/noextreg.{s,d}: New. + * testsuite/gas/i386/i386.exp: Run new test. + 2017-11-15 Jan Beulich * testsuite/gas/i386/x86-64-reg.s: Add extended byte reg tests. diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 7a8b642432b..a053676df89 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -182,6 +182,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "noavx-4" run_list_test "noavx512-1" "-al" run_list_test "noavx512-2" "-al" + run_dump_test "noextreg" run_dump_test "xsave" run_dump_test "xsave-intel" run_dump_test "aes" diff --git a/gas/testsuite/gas/i386/noextreg.d b/gas/testsuite/gas/i386/noextreg.d new file mode 100644 index 00000000000..cb181b17ee5 --- /dev/null +++ b/gas/testsuite/gas/i386/noextreg.d @@ -0,0 +1,12 @@ +#objdump: -dw +#name: ix86 no extended registers + +.*: file format .* + +Disassembly of section .text: + +0+ : +[ ]*[a-f0-9]+: c4 e3 79 68 00 00 vfmaddps %xmm0,\(%eax\),%xmm0,%xmm0 +[ ]*[a-f0-9]+: c4 e3 79 68 00 0f vfmaddps %xmm0,\(%eax\),%xmm0,%xmm0 +[ ]*[a-f0-9]+: c3 ret[ ]* +#pass diff --git a/gas/testsuite/gas/i386/noextreg.s b/gas/testsuite/gas/i386/noextreg.s new file mode 100644 index 00000000000..229b994a994 --- /dev/null +++ b/gas/testsuite/gas/i386/noextreg.s @@ -0,0 +1,10 @@ + .intel_syntax noprefix + .text +ix86: + vfmaddps xmm0, xmm0, [eax], xmm0 + .byte 0xc4, 0xe3, 0x79, 0x68, 0x00, 0x0f # vfmaddps xmm0, xmm0, [eax], xmm0 + + ret + + .type ix86, @function + .size ix86, . - ix86 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e8af8b2eda3..674736ba846 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2017-11-15 Jan Beulich + + * i386-dis.c (VEXI4_Fixup, VexI4): Delete. + (prefix_table, xop_table, vex_len_table): Remove VexI4 uses. + (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd + pass. + (OP_REG_VexI4): Drop low 4 bits check. + 2017-11-15 Jan Beulich * i386-reg.tbl (axl): Remove Acc and Byte. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index b4d23050581..6a5a7f1bd6a 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -95,7 +95,6 @@ static void OP_XMM_VexW (int, int); static void OP_Rounding (int, int); static void OP_REG_VexI4 (int, int); static void PCLMUL_Fixup (int, int); -static void VEXI4_Fixup (int, int); static void VZERO_Fixup (int, int); static void VCMP_Fixup (int, int); static void VPCMP_Fixup (int, int); @@ -423,7 +422,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Vex128 { OP_VEX, vex128_mode } #define Vex256 { OP_VEX, vex256_mode } #define VexGdq { OP_VEX, dq_mode } -#define VexI4 { VEXI4_Fixup, 0} #define EXdVex { OP_EX_Vex, d_mode } #define EXdVexS { OP_EX_Vex, d_swap_mode } #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } @@ -6748,28 +6746,28 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A5D */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A5E */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A5F */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A60 */ @@ -6805,14 +6803,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A69 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A6A */ @@ -6833,14 +6831,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A6D */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A6E */ @@ -6861,14 +6859,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A79 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A7A */ @@ -6889,7 +6887,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, }, @@ -6897,7 +6895,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A7E */ @@ -7857,9 +7855,9 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, /* 88 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7867,17 +7865,17 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, /* 90 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, /* 98 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7885,16 +7883,16 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, /* a0 */ { Bad_Opcode }, { Bad_Opcode }, - { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, /* a8 */ { Bad_Opcode }, @@ -7912,7 +7910,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, /* b8 */ { Bad_Opcode }, @@ -10144,42 +10142,42 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A6A_P_2 */ { - { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, + { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, /* VEX_LEN_0F3A6B_P_2 */ { - { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, + { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, /* VEX_LEN_0F3A6E_P_2 */ { - { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, + { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, /* VEX_LEN_0F3A6F_P_2 */ { - { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, + { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, /* VEX_LEN_0F3A7A_P_2 */ { - { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, + { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, /* VEX_LEN_0F3A7B_P_2 */ { - { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, + { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, /* VEX_LEN_0F3A7E_P_2 */ { - { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, + { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, /* VEX_LEN_0F3A7F_P_2 */ { - { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, + { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, /* VEX_LEN_0F3ADF_P_2 */ @@ -17403,8 +17401,6 @@ OP_EX_VexW (int bytemode, int sizeflag) if (!vex_w_done) { - vex_w_done = 1; - /* Skip mod/rm byte. */ MODRM_CHECK; codep++; @@ -17419,16 +17415,10 @@ OP_EX_VexW (int bytemode, int sizeflag) } OP_EX_VexReg (bytemode, sizeflag, reg); -} -static void -VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, - int sizeflag ATTRIBUTE_UNUSED) -{ - /* Skip the immediate byte and check for invalid bits. */ - FETCH_DATA (the_info, codep + 1); - if (*codep++ & 0xf) - BadOp (); + if (vex_w_done) + codep++; + vex_w_done = 1; } static void @@ -17443,9 +17433,6 @@ OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) if (bytemode != x_mode) abort (); - if (reg & 0xf) - BadOp (); - reg >>= 4; if (reg > 7 && address_mode != mode_64bit) BadOp (); -- 2.30.2