From 3a2e6117f4c5712578834625ca4550df4bce60c2 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 14 Nov 2015 11:55:21 +0100
Subject: [PATCH] soc/interconnect/stream: add Cast and others small fixes

---
 litex/soc/integration/soc_core.py        |  7 +++--
 litex/soc/interconnect/stream.py         | 38 ++++++++++++++++++++----
 litex/soc/interconnect/wishbonebridge.py |  2 +-
 3 files changed, 37 insertions(+), 10 deletions(-)

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index bb1d2bf0..e7cc8ca8 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -195,9 +195,10 @@ class SoCCore(Module):
             self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory)
 
         # Interrupts
-        for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
-            if hasattr(self, k):
-                self.comb += self.cpu_or_bridge.interrupt[v].eq(getattr(self, k).ev.irq)
+        if hasattr(self.cpu_or_bridge, "interrupt"):
+            for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
+                if hasattr(self, k):
+                    self.comb += self.cpu_or_bridge.interrupt[v].eq(getattr(self, k).ev.irq)
 
     def build(self, *args, **kwargs):
         self.platform.build(self, *args, **kwargs)
diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index cceb8c42..f0a78101 100644
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -74,7 +74,7 @@ class _FIFOWrapper(Module):
         self.source = Source(layout)
         self.busy = Signal()
 
-        ###
+        # # #
 
         description = self.sink.description
         fifo_layout = [("payload", description.payload_layout)]
@@ -161,6 +161,12 @@ class Demultiplexer(Module):
 from copy import copy
 from litex.gen.util.misc import xdir
 
+def _rawbits_layout(l):
+    if isinstance(l, int):
+        return [("rawbits", l)]
+    else:
+        return l
+
 def pack_layout(l, n):
     return [("chunk"+str(i), l) for i in range(n)]
 
@@ -256,6 +262,26 @@ class Buffer(PipelinedActor):
                 self.q.param.eq(self.d.param)
             )
 
+
+class Cast(CombinatorialActor):
+    def __init__(self, layout_from, layout_to, reverse_from=False, reverse_to=False):
+        self.sink = Sink(_rawbits_layout(layout_from))
+        self.source = Source(_rawbits_layout(layout_to))
+        CombinatorialActor.__init__(self)
+
+        # # #
+
+        sigs_from = self.sink.payload.flatten()
+        if reverse_from:
+            sigs_from = list(reversed(sigs_from))
+        sigs_to = self.source.payload.flatten()
+        if reverse_to:
+            sigs_to = list(reversed(sigs_to))
+        if sum(len(s) for s in sigs_from) != sum(len(s) for s in sigs_to):
+            raise TypeError
+        self.comb += Cat(*sigs_to).eq(Cat(*sigs_from))
+
+
 class Unpack(Module):
     def __init__(self, n, layout_to, reverse=False):
         self.source = source = Source(layout_to)
@@ -265,7 +291,7 @@ class Unpack(Module):
 
         self.busy = Signal()
 
-        ###
+        # # #
 
         mux = Signal(max=n)
         first = Signal()
@@ -306,7 +332,7 @@ class Pack(Module):
         self.source = source = Source(description_to)
         self.busy = Signal()
 
-        ###
+        # # #
 
         demux = Signal(max=n)
 
@@ -364,7 +390,7 @@ class Chunkerize(CombinatorialActor):
         self.source = Source(layout_to)
         CombinatorialActor.__init__(self)
 
-        ###
+        # # #
 
         for i in range(n):
             chunk = n-i-1 if reverse else i
@@ -387,7 +413,7 @@ class Unchunkerize(CombinatorialActor):
         self.source = Source(layout_to)
         CombinatorialActor.__init__(self)
 
-        ###
+        # # #
 
         for i in range(n):
             chunk = n-i-1 if reverse else i
@@ -403,7 +429,7 @@ class Converter(Module):
         self.source = Source(layout_to)
         self.busy = Signal()
 
-        ###
+        # # #
 
         width_from = len(self.sink.payload.raw_bits())
         width_to = len(self.source.payload.raw_bits())
diff --git a/litex/soc/interconnect/wishbonebridge.py b/litex/soc/interconnect/wishbonebridge.py
index 6e39b979..826b5716 100644
--- a/litex/soc/interconnect/wishbonebridge.py
+++ b/litex/soc/interconnect/wishbonebridge.py
@@ -56,7 +56,7 @@ class WishboneStreamingBridge(Module):
             )
         ]
 
-        fsm = InsertReset(FSM(reset_state="IDLE"))
+        fsm = ResetInserter()(FSM(reset_state="IDLE"))
         timer = WaitTimer(clk_freq//10)
         self.submodules += fsm, timer
         self.comb += [
-- 
2.30.2