From 3a3558acce25807d6ce75280cc3f43aeb52974df Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 16 Jul 2018 15:56:12 +0200 Subject: [PATCH] ecp5: Fixing miscellaneous sim model issues Signed-off-by: David Shah --- techlibs/ecp5/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index cf1446a52..1700694e8 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -232,13 +232,13 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q); always @(posedge muxclk, posedge muxlsr) if (muxlsr) Q <= srval; - else + else if (muxce) Q <= DI; end else begin always @(posedge muxclk) if (muxlsr) Q <= srval; - else + else if (muxce) Q <= DI; end endgenerate -- 2.30.2