From 3a38626556ffe4a96df3f7f1d4e7aa98e4bb2e43 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 21 Mar 2015 18:22:26 +0100 Subject: [PATCH] mibuild/platforms: add minispartan6 (from Matt O'Gorman) --- mibuild/platforms/minispartan6.py | 119 ++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 mibuild/platforms/minispartan6.py diff --git a/mibuild/platforms/minispartan6.py b/mibuild/platforms/minispartan6.py new file mode 100644 index 00000000..28d05686 --- /dev/null +++ b/mibuild/platforms/minispartan6.py @@ -0,0 +1,119 @@ +# This file is Copyright (c) 2015 Matt O'Gorman +# License: BSD + +from mibuild.generic_platform import * +from mibuild.crg import SimpleCRG +from mibuild.xilinx_ise import XilinxISEPlatform +from mibuild.programmer import XC3SProg + +_io = [ + ("user_led", 0, Pins("P11"), IOStandard("LVTTL"), Misc("SLEW=SLOW")), + ("user_led", 1, Pins("N9"), IOStandard("LVTTL"), Misc("SLEW=SLOW")), + ("user_led", 2, Pins("M9"), IOStandard("LVTTL"), Misc("SLEW=SLOW")), + ("user_led", 3, Pins("P9"), IOStandard("LVTTL"), Misc("SLEW=SLOW")), + ("user_led", 4, Pins("T8"), IOStandard("LVTTL"), Misc("SLEW=SLOW")), + ("user_led", 5, Pins("N8"), IOStandard("LVTTL"), Misc("SLEW=SLOW")), + ("user_led", 6, Pins("P8"), IOStandard("LVTTL"), Misc("SLEW=SLOW")), + ("user_led", 7, Pins("P7"), IOStandard("LVTTL"), Misc("SLEW=SLOW")), + + ("user_sw", 0, Pins("L1"), IOStandard("LVTTL"), Misc("PULLUP")), + ("user_sw", 1, Pins("L3"), IOStandard("LVTTL"), Misc("PULLUP")), + ("user_sw", 2, Pins("L4"), IOStandard("LVTTL"), Misc("PULLUP")), + ("user_sw", 3, Pins("L5"), IOStandard("LVTTL"), Misc("PULLUP")), + + ("clk32", 0, Pins("K3"), IOStandard("LVCMOS33")), + ("clk50", 0, Pins("J4"), IOStandard("LVCMOS33")), + + ("spiflash", 0, + Subsignal("cs_n", Pins("T3"), IOStandard("LVTTL")), + Subsignal("clk", Pins("R11"), IOStandard("LVTTL")), + Subsignal("mosi", Pins("T10"), IOStandard("LVTTL")), + Subsignal("miso", Pins("P10"), IOStandard("LVTTL")) + ), + + ("adc", 0, + Subsignal("cs_n", Pins("F6"), IOStandard("LVTTL")), + Subsignal("clk", Pins("G6"), IOStandard("LVTTL")), + Subsignal("mosi", Pins("H4"), IOStandard("LVTTL")), + Subsignal("miso", Pins("H5"), IOStandard("LVTTL")) + ), + + ("serial", 0, + Subsignal("tx", Pins("N3"), IOStandard("LVTTL")), + Subsignal("rx", Pins("N1"), IOStandard("LVTTL")) + ), + + ("audio", 0, + Subsignal("a0", Pins("B8"), IOStandard("LVTTL")), + Subsignal("a1", Pins("A8"), IOStandard("LVTTL")) + ), + + ("sdram_clock", 0, Pins("G16"), IOStandard("LVTTL")), + ("sdram", 0, + Subsignal("a", Pins("T15 R16 P15 P16 N16 M15 M16 L16 K15 K16 R15 J16 H15")), + Subsignal("dq", Pins("T13 T12 R12 T9 R9 T7 R7 T6 F16 E15 E16 D16 B16 B15 C16 C15")), + Subsignal("we_n", Pins("R5")), + Subsignal("ras_n", Pins("R2")), + Subsignal("cas_n", Pins("T4")), + Subsignal("cs_n", Pins("R1")), + Subsignal("cke", Pins("H16")), + Subsignal("ba", Pins("R14 T14")), + Subsignal("dm", Pins("T5 F15")) + ), + + ("sd", 0, + Subsignal("sck", Pins("L12")), + Subsignal("d3", Pins("K12")), + Subsignal("d", Pins("M10")), + Subsignal("d1", Pins("L10")), + Subsignal("d2", Pins("J11")), + Subsignal("cmd", Pins("K11")) + ), + + ("dvi_in", 0, + Subsignal("clk_p", Pins("C9"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("A9"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("C7"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("A7"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("B6"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("A6"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("B5"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("A5"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("C1"), IOStandard("LVTTL")), + Subsignal("sda", Pins("B1"), IOStandard("LVTTL")) + ), + + ("dvi_out", 0, + Subsignal("clk_p", Pins("B14"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("A14"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("C13"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("A13"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("B12"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("A12"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("C11"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("A11"), IOStandard("TMDS_33")) + ) +] + +_connectors = [ + ("A", "E7 C8 D8 E8 D9 A10 B10 C10 E10 F9 F10 D11"), + ("B", "E11 D14 D12 E12 E13 F13 F12 F14 G12 H14 J14"), + ("C", "J13 J12 K14 L14 L13 M14 M13 N14 M12 N12 P12 M11"), + ("D", "D6 C6 E6 C5"), + ("E", "D5 A4 G5 A3 B3 A2 B2 C3 C2 D3 D1 E3"), + ("F", "E2 E1 E4 F4 F5 G3 F3 G1 H3 H1 H2 J1") +] + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc6slx9-3-ftg256", _io, + lambda p: SimpleCRG(p, "clk50", None), _connectors) + + def create_programmer(self): + return XC3SProg("minispartan6", "bscan_spi_minispartan6.bit") + + def do_finalize(self, fragment): + try: + self.add_period_constraint(self.lookup_request("50"), 50) + except ConstraintError: + pass \ No newline at end of file -- 2.30.2