From 3a390733027584071d0cd3b2d99c738ce6f1a829 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 17:10:43 -0700 Subject: [PATCH] Set more ports explicitly --- passes/pmgen/xilinx_dsp.cc | 2 ++ techlibs/xilinx/dsp_map.v | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index ae8cd64da..e0c7823ed 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -44,6 +44,8 @@ static Cell* addDsp(Module *module) { cell->setParam("\\OPMODEREG", 0); cell->setParam("\\PREG", 0); cell->setParam("\\USE_MULT", Const("NONE")); + cell->setParam("\\USE_SIMD", Const("ONE48")); + cell->setParam("\\USE_DPORT", Const("FALSE")); cell->setPort("\\D", Const(0, 24)); cell->setPort("\\INMODE", Const(0, 5)); diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index cc37f0085..8901b215b 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -25,7 +25,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .OPMODEREG(0), .PREG(0), .USE_MULT("MULTIPLY"), - .USE_SIMD("ONE48") + .USE_SIMD("ONE48"), + .USE_DPORT("FALSE") ) _TECHMAP_REPLACE_ ( //Data path .A({{5{A[24]}}, A}), -- 2.30.2