From 3a404be62a7b7fcc435857e20aa6c528f373b81c Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Mon, 14 Aug 2017 17:15:56 -0700 Subject: [PATCH] Updated PGEN model to have level triggered reset (matches actual hardware behavior --- techlibs/greenpak4/cells_sim_digital.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 5d9d67750..6fba941a0 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -741,10 +741,10 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT); localparam COUNT_MAX = PATTERN_LEN - 1'h1; reg[3:0] count = 0; - always @(posedge CLK) begin - if(!nRST) begin - count <= COUNT_MAX; - end + always @(posedge CLK, negedge nRST) begin + + if(!nRST) + count <= 0; else begin count <= count - 1'h1; -- 2.30.2